Initial import of ViperOS
This commit is contained in:
Viper
251
VKernel/Kernel/drivers/core/cpu/apic.py
Normal file
251
VKernel/Kernel/drivers/core/cpu/apic.py
Normal file
@@ -0,0 +1,251 @@
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import asm
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import intr.gdt as gdt
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import intr.idt as idt
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import drivers.serial.uart.serial as serial
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import drivers.core.cpu.cpu as cpu
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import mm.mm as mm
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import platform.pch.timer as timer
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import viperlib
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import t, c
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IA32_APIC_BASE: t.CDefine = 0x1B
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APIC_BASE_MSR_ENABLE: t.CDefine = 0x800
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APIC_BASE_ADDR_MASK: t.CDefine = 0xFFFFF000
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LAPIC_ID: t.CDefine = 0x020
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LAPIC_VERSION: t.CDefine = 0x030
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LAPIC_TPR: t.CDefine = 0x080
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LAPIC_EOI: t.CDefine = 0x0B0
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LAPIC_LDR: t.CDefine = 0x0D0
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LAPIC_SVR: t.CDefine = 0x0F0
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LAPIC_ISR0: t.CDefine = 0x100
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LAPIC_ICR_LOW: t.CDefine = 0x300
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LAPIC_ICR_HIGH: t.CDefine = 0x310
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LAPIC_LVT_TIMER: t.CDefine = 0x320
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LAPIC_LVT_LINT0: t.CDefine = 0x350
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LAPIC_LVT_LINT1: t.CDefine = 0x360
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LAPIC_LVT_ERROR: t.CDefine = 0x370
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LAPIC_TIMER_INIT: t.CDefine = 0x380
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LAPIC_TIMER_CURRENT: t.CDefine = 0x390
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LAPIC_TIMER_DIVIDE: t.CDefine = 0x3E0
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LAPIC_SVR_ENABLE: t.CDefine = 0x100
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LAPIC_LVT_MASKED: t.CDefine = 0x10000
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LAPIC_LVT_DELIVERY_EXTINT: t.CDefine = 0x700
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LAPIC_LVT_DELIVERY_NMI: t.CDefine = 0x400
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LAPIC_LVT_TIMER_PERIODIC: t.CDefine = 0x20000
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LAPIC_ICR_INIT: t.CDefine = 0x500
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LAPIC_ICR_STARTUP: t.CDefine = 0x600
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LAPIC_ICR_ASSERT: t.CDefine = 0x4000
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LAPIC_ICR_DEASSERT: t.CDefine = 0x8000
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LAPIC_ICR_LEVEL: t.CDefine = 0x8000
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MAX_CPUS: t.CDefine = 8
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AP_TRAMPOLINE_ADDR: t.CDefine = 0x7000
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_lapic_base: t.CStatic | t.CUInt64T = 0
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_cpu_count: t.CStatic | t.CUInt32T = 1
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_bsp_lapic_id: t.CStatic | t.CUInt32T = 0
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_ap_ready: t.CStatic | t.CUInt32T = 0
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def read(offset: t.CUInt32T) -> t.CUInt32T:
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addr: t.CUInt64T = _lapic_base + t.CUInt64T(offset)
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return c.Deref(t.CUInt32T(addr, t.CPtr))
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def write(offset: t.CUInt32T, value: t.CUInt32T):
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addr: t.CUInt64T = _lapic_base + t.CUInt64T(offset)
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c.Set(c.Deref(t.CUInt32T(addr, t.CPtr)), value)
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def eoi():
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write(LAPIC_EOI, 0)
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def get_id() -> t.CUInt32T:
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return read(LAPIC_ID) >> 24
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@c.Attribute(t.attr.noinline)
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def init():
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global _lapic_base, _bsp_lapic_id
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msr_val: t.CUInt64T = cpu.msr_read(IA32_APIC_BASE)
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_lapic_base = msr_val & APIC_BASE_ADDR_MASK
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cpu.msr_write(IA32_APIC_BASE, msr_val | APIC_BASE_MSR_ENABLE)
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_bsp_lapic_id = read(LAPIC_ID) >> 24
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write(LAPIC_SVR, LAPIC_SVR_ENABLE | 0xFF)
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write(LAPIC_TPR, 0)
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write(LAPIC_LVT_TIMER, LAPIC_LVT_MASKED)
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write(LAPIC_LVT_LINT0, LAPIC_LVT_DELIVERY_EXTINT)
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write(LAPIC_LVT_LINT1, LAPIC_LVT_DELIVERY_NMI)
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write(LAPIC_LVT_ERROR, LAPIC_LVT_MASKED)
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write(LAPIC_TIMER_DIVIDE, 0x0B)
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write(LAPIC_LDR, 0x01000000)
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eoi()
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@c.Attribute(t.attr.noinline)
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def detect_cpu_count() -> t.CUInt32T:
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res: cpu.cpuid_result
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cpu.cpuid(0, c.Addr(res))
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max_leaf: t.CUInt32T = res.eax
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if max_leaf >= 0x0B:
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cpu.cpuid_sub(0x0B, 0, c.Addr(res))
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num_threads: t.CUInt32T = res.ebx & 0xFFFF
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if num_threads > 0 and num_threads <= MAX_CPUS:
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return num_threads
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cpu.cpuid(1, c.Addr(res))
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if res.edx & cpu.CPU_FEATURE_HTT:
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count: t.CUInt32T = (res.ebx >> 16) & 0xFF
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if count > 0 and count <= MAX_CPUS:
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return count
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return 1
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def _wait_icr():
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timeout: t.CUInt32T = 1000000
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while timeout > 0:
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val: t.CUInt32T = read(LAPIC_ICR_LOW)
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if (val & (1 << 12)) == 0:
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return
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timeout -= 1
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def _send_ipi(apic_id: t.CUInt32T, vector: t.CUInt32T, delivery_mode: t.CUInt32T):
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_wait_icr()
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write(LAPIC_ICR_HIGH, apic_id << 24)
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write(LAPIC_ICR_LOW, vector | delivery_mode | LAPIC_ICR_LEVEL | LAPIC_ICR_ASSERT)
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_wait_icr()
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def ap_entry():
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global _ap_ready
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my_id: t.CUInt32T = get_id()
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buf: t.CArray[t.CChar, 64]
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viperlib.snprintf(c.Addr(buf), 64, "[AP] core %u started (lapic=%u)\n", my_id, my_id)
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serial.puts(buf)
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_ap_ready = 1
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while True:
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asm.sti()
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asm.hlt()
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_trampoline_bin: t.CStatic | t.CArray[t.CUInt8T, 128] = [
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0xFA, # cli
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0x31, 0xC0, # xor ax, ax
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x0F, 0x01, 0x16, 0x00, 0x7E, # lgdt [0x7E00]
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0x0F, 0x20, 0xC0, # mov eax, cr0
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0x83, 0xC8, 0x01, # or eax, 1
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0x0F, 0x22, 0xC0, # mov cr0, eax
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0xEA, 0x1A, 0x07, 0x00, 0x00, 0x08, 0x00, # jmp 0x08:0x701A
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# 32-bit 保护模式开始
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0xB8, 0x10, 0x00, 0x00, 0x00, # mov ax, 0x10
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x8E, 0xE0, # mov fs, ax
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0x8E, 0xE8, # mov gs, ax
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0x8E, 0xD0, # mov ss, ax
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0x0F, 0x20, 0xE0, # mov eax, cr4
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0x83, 0xC8, 0x20, # or eax, 0x20 (PAE)
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0x0F, 0x22, 0xE0, # mov cr4, eax
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0x8B, 0x04, 0x25, 0x00, 0x7F, 0x00, 0x00, # mov eax, [0x7F00]
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0x0F, 0x22, 0xD8, # mov cr3, eax
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0xB9, 0x80, 0x00, 0x00, 0xC0, # mov ecx, 0xC0000080 (EFER)
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0x0F, 0x32, # rdmsr
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0x83, 0xC8, 0x00, 0x01, 0x00, 0x00, # or eax, 0x100 (LME)
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0x0F, 0x79, # wrmsr
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0x0F, 0x20, 0xC0, # mov eax, cr0
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0x0D, 0x00, 0x00, 0x00, 0x80, # or eax, 0x80000000 (PG)
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0x0F, 0x22, 0xC0, # mov cr0, eax
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0xEA, 0x5A, 0x07, 0x00, 0x00, 0x08, 0x00, # jmp 0x08:0x705A
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# 64-bit 长模式开始
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0x48, 0x8B, 0x24, 0x25, 0x08, 0x7F, 0x00, 0x00, # mov rsp, [0x7F08]
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0x0F, 0x01, 0x16, 0x10, 0x7F, # lgdt [0x7F10]
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0x0F, 0x01, 0x1E, 0x20, 0x7F, # lidt [0x7F20]
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0xB8, 0x10, 0x00, 0x00, 0x00, # mov ax, 0x10
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x8E, 0xE0, # mov fs, ax
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0x8E, 0xE8, # mov gs, ax
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0x8E, 0xD0, # mov ss, ax
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0x48, 0x8B, 0x04, 0x25, 0x28, 0x7F, 0x00, 0x00, # mov rax, [0x7F28]
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0xFF, 0xE0 # jmp rax
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]
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def _setup_trampoline(entry_addr: t.CUInt64T, stack_addr: t.CUInt64T, cr3_val: t.CUInt64T):
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dest: t.CUInt8T | t.CPtr = t.CUInt8T(AP_TRAMPOLINE_ADDR, t.CPtr)
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src: t.CUInt8T | t.CPtr = c.Addr(_trampoline_bin)
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i: t.CInt
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for i in range(128):
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c.Set(c.Deref(dest + t.CUInt64T(i)), c.Deref(src + t.CUInt64T(i)))
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gdt_ptr_addr: t.CUInt64T = AP_TRAMPOLINE_ADDR + 0x0E00
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c.Set(c.Deref(t.CUInt16T(gdt_ptr_addr, t.CPtr)), t.CUInt16T(23))
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c.Set(c.Deref(t.CUInt64T(gdt_ptr_addr + 2, t.CPtr)), t.CUInt64T(AP_TRAMPOLINE_ADDR + 0x0E10))
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gdt_addr: t.CUInt64T = AP_TRAMPOLINE_ADDR + 0x0E10
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c.Set(c.Deref(t.CUInt64T(gdt_addr, t.CPtr)), t.CUInt64T(0))
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c.Set(c.Deref(t.CUInt64T(gdt_addr + 8, t.CPtr)), t.CUInt64T(0x00AF9A000000FFFF))
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c.Set(c.Deref(t.CUInt64T(gdt_addr + 16, t.CPtr)), t.CUInt64T(0x00CF92000000FFFF))
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c.Set(c.Deref(t.CUInt32T(AP_TRAMPOLINE_ADDR + 0x0F00, t.CPtr)), t.CUInt32T(cr3_val))
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c.Set(c.Deref(t.CUInt64T(AP_TRAMPOLINE_ADDR + 0x0F08, t.CPtr)), stack_addr)
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gp_addr: t.CUInt64T = t.CUInt64T(c.Addr(gdt.gp))
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gdt_base: t.CUInt64T = c.Deref(t.CUInt64T(gp_addr + 2, t.CPtr))
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gdt_limit: t.CUInt16T = c.Deref(t.CUInt16T(gp_addr, t.CPtr))
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c.Set(c.Deref(t.CUInt16T(AP_TRAMPOLINE_ADDR + 0x0F10, t.CPtr)), gdt_limit)
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c.Set(c.Deref(t.CUInt64T(AP_TRAMPOLINE_ADDR + 0x0F12, t.CPtr)), gdt_base)
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idt_addr: t.CUInt64T = t.CUInt64T(c.Addr(idt.idp))
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idt_base: t.CUInt64T = c.Deref(t.CUInt64T(idt_addr + 2, t.CPtr))
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idt_limit: t.CUInt16T = c.Deref(t.CUInt16T(idt_addr, t.CPtr))
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c.Set(c.Deref(t.CUInt16T(AP_TRAMPOLINE_ADDR + 0x0F20, t.CPtr)), idt_limit)
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c.Set(c.Deref(t.CUInt64T(AP_TRAMPOLINE_ADDR + 0x0F22, t.CPtr)), idt_base)
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c.Set(c.Deref(t.CUInt64T(AP_TRAMPOLINE_ADDR + 0x0F28, t.CPtr)), entry_addr)
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def start_aps():
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global _cpu_count, _ap_ready
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if _cpu_count <= 1: return
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cr3_val: t.CUInt64T = 0
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c.Asm(f"""mov rax, cr3
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mov {c.AsmOut(cr3_val, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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stack_size: t.CUInt64T = 8192
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i: t.CUInt32T
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for i in range(1, _cpu_count):
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_ap_ready = 0
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stack: t.CVoid | t.CPtr = mm.malloc(stack_size)
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if stack is None: continue
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stack_top: t.CUInt64T = t.CUInt64T(stack) + stack_size
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stack_top = stack_top & ~t.CUInt64T(15)
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_setup_trampoline(t.CUInt64T(ap_entry), stack_top, cr3_val)
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_send_ipi(i, 0, LAPIC_ICR_INIT)
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timer.timer_msleep(10)
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_send_ipi(i, (AP_TRAMPOLINE_ADDR >> 12) & 0xFF, LAPIC_ICR_STARTUP)
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timer.timer_msleep(1)
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_send_ipi(i, (AP_TRAMPOLINE_ADDR >> 12) & 0xFF, LAPIC_ICR_STARTUP)
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wait: t.CUInt32T = 0
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while _ap_ready == 0 and wait < 5000:
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timer.timer_msleep(1)
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wait += 1
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def early_init():
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global _cpu_count, _bsp_lapic_id
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features: t.CUInt32T = cpu.detect_features_static()
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if features & cpu.CPU_FEATURE_APIC:
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init()
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_cpu_count = detect_cpu_count()
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else:
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_cpu_count = 1
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def get_cpu_count() -> t.CUInt32T:
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return _cpu_count
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def get_lapic_id() -> t.CUInt32T:
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return get_id()
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346
VKernel/Kernel/drivers/core/cpu/cpu.py
Normal file
346
VKernel/Kernel/drivers/core/cpu/cpu.py
Normal file
@@ -0,0 +1,346 @@
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import fpu
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import asm
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import intr.gdt as gdt
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import string
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import t, c
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IA32_KERNEL_GS_BASE: t.CDefine = 0xC0000102
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KERN_STACK_SIZE: t.CDefine = 8192
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CPU_FEATURE_FPU: t.CDefine = (1 << 0)
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CPU_FEATURE_PSE: t.CDefine = (1 << 1)
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CPU_FEATURE_MSR: t.CDefine = (1 << 2)
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CPU_FEATURE_PAE: t.CDefine = (1 << 3)
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CPU_FEATURE_MCE: t.CDefine = (1 << 4)
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CPU_FEATURE_CX8: t.CDefine = (1 << 5)
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CPU_FEATURE_APIC: t.CDefine = (1 << 6)
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CPU_FEATURE_SEP: t.CDefine = (1 << 7)
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CPU_FEATURE_MTRR: t.CDefine = (1 << 8)
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CPU_FEATURE_PGE: t.CDefine = (1 << 9)
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CPU_FEATURE_MCA: t.CDefine = (1 << 10)
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CPU_FEATURE_CMOV: t.CDefine = (1 << 11)
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CPU_FEATURE_PAT: t.CDefine = (1 << 12)
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CPU_FEATURE_PSE36: t.CDefine = (1 << 13)
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CPU_FEATURE_PSN: t.CDefine = (1 << 14)
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CPU_FEATURE_CLFSH: t.CDefine = (1 << 15)
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CPU_FEATURE_DS: t.CDefine = (1 << 16)
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CPU_FEATURE_ACPI: t.CDefine = (1 << 17)
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CPU_FEATURE_MMX: t.CDefine = (1 << 18)
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CPU_FEATURE_FXSR: t.CDefine = (1 << 19)
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CPU_FEATURE_SSE: t.CDefine = (1 << 20)
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CPU_FEATURE_SSE2: t.CDefine = (1 << 21)
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CPU_FEATURE_SS: t.CDefine = (1 << 22)
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CPU_FEATURE_HTT: t.CDefine = (1 << 23)
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CPU_FEATURE_TM: t.CDefine = (1 << 24)
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CPU_FEATURE_PBE: t.CDefine = (1 << 25)
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class cpu_info(t.CStruct):
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vendor_id: t.CArray[t.CChar, 13]
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brand_string: t.CArray[t.CChar, 48]
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features: t.CUInt32T
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family: t.CUInt32T
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model: t.CUInt32T
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stepping: t.CUInt32T
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cpu_type: t.CUInt32T
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ext_model: t.CUInt32T
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ext_family: t.CUInt32T
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cpu_freq: t.CUInt64T
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@c.Attribute(t.attr.packed)
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class _tss:
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reserved0: t.CUInt64T
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rsp0: t.CUInt64T
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rsp1: t.CUInt64T
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rsp2: t.CUInt64T
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reserved1: t.CUInt64T
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ist1: t.CUInt64T
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ist2: t.CUInt64T
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ist3: t.CUInt64T
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ist4: t.CUInt64T
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ist5: t.CUInt64T
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ist6: t.CUInt64T
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ist7: t.CUInt64T
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reserved2: t.CUInt64T
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reserved3: t.CUInt16T
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io_map_base: t.CUInt16T
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class cpuid_result(t.CStruct):
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eax: t.CUInt32T
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ebx: t.CUInt32T
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ecx: t.CUInt32T
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edx: t.CUInt32T
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@c.Attribute(t.attr.naked)
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def _rdmsr_naked():
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c.Asm(f"""rdmsr
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shl rdx, 32
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or rax, rdx
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RDX])
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@c.Attribute(t.attr.naked)
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def _wrmsr_naked():
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# msr_write sets ecx=msr, r8=value. wrmsr needs ECX=msr, EDX:EAX=value.
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# Old code did `mov rax,rcx` (rax=msr) which wrote (value>>32):msr to MSR,
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# corrupting IA32_KERNEL_GS_BASE -> swapgs -> #GP on gs:[0]. Fixed below.
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c.Asm(f"""mov rax, r8
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mov rdx, r8
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shr rdx, 32
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wrmsr
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RDX])
|
||||
|
||||
def msr_read(msr: t.CUInt32T) -> t.CUInt64T:
|
||||
result: t.CUInt64T = 0
|
||||
func: t.CVoid | t.CPtr = _rdmsr_naked
|
||||
c.Asm(f"""mov ecx, {c.AsmInp(msr, t.ASM_DESCR.REG_ANY)}
|
||||
call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}
|
||||
mov {c.AsmOut(result, t.ASM_DESCR.OUTPUT_REG)}, rax""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX, t.ASM_DESCR.CLOBBER_RDX])
|
||||
return result
|
||||
|
||||
def msr_write(msr: t.CUInt32T, value: t.CUInt64T):
|
||||
func: t.CVoid | t.CPtr = _wrmsr_naked
|
||||
c.Asm(f"""mov ecx, {c.AsmInp(msr, t.ASM_DESCR.REG_ANY)}
|
||||
mov r8, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
|
||||
call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX, t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8])
|
||||
|
||||
@c.Attribute(t.attr.naked)
|
||||
def _cpuid_naked():
|
||||
c.Asm(f"""push rbx
|
||||
mov eax, ecx
|
||||
cpuid
|
||||
mov dword ptr [rdx], eax
|
||||
mov dword ptr [rdx + 4], ebx
|
||||
mov dword ptr [rdx + 8], ecx
|
||||
mov dword ptr [rdx + 12], edx
|
||||
pop rbx
|
||||
ret""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
|
||||
t.ASM_DESCR.CLOBBER_RDX])
|
||||
|
||||
@c.Attribute(t.attr.naked)
|
||||
def _cpuid_sub_naked():
|
||||
c.Asm(f"""push rbx
|
||||
mov eax, ecx
|
||||
mov ecx, r8d
|
||||
cpuid
|
||||
mov dword ptr [rdx], eax
|
||||
mov dword ptr [rdx + 4], ebx
|
||||
mov dword ptr [rdx + 8], ecx
|
||||
mov dword ptr [rdx + 12], edx
|
||||
pop rbx
|
||||
ret""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
|
||||
t.ASM_DESCR.CLOBBER_RDX])
|
||||
|
||||
@c.Attribute(t.attr.noinline)
|
||||
def cpuid(leaf: t.CUInt32T, out: cpuid_result | t.CPtr):
|
||||
func: t.CVoid | t.CPtr = _cpuid_naked
|
||||
c.Asm(f"""mov ecx, {c.AsmInp(leaf, t.ASM_DESCR.REG_ANY)}
|
||||
mov rdx, {c.AsmInp(out, t.ASM_DESCR.REG_ANY)}
|
||||
call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
|
||||
t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8,
|
||||
t.ASM_DESCR.CLOBBER_R9, t.ASM_DESCR.CLOBBER_R10,
|
||||
t.ASM_DESCR.CLOBBER_R11])
|
||||
|
||||
@c.Attribute(t.attr.noinline)
|
||||
def cpuid_sub(leaf: t.CUInt32T, sub: t.CUInt32T, out: cpuid_result | t.CPtr):
|
||||
func: t.CVoid | t.CPtr = _cpuid_sub_naked
|
||||
c.Asm(f"""mov ecx, {c.AsmInp(leaf, t.ASM_DESCR.REG_ANY)}
|
||||
mov r8d, {c.AsmInp(sub, t.ASM_DESCR.REG_ANY)}
|
||||
mov rdx, {c.AsmInp(out, t.ASM_DESCR.REG_ANY)}
|
||||
call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
|
||||
op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
|
||||
t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8,
|
||||
t.ASM_DESCR.CLOBBER_R9, t.ASM_DESCR.CLOBBER_R10,
|
||||
t.ASM_DESCR.CLOBBER_R11])
|
||||
|
||||
@c.Attribute(t.attr.noinline)
|
||||
def detect_features_static() -> t.CUInt32T:
|
||||
features: t.CUInt32T = 0
|
||||
res: cpuid_result
|
||||
cpuid(1, c.Addr(res))
|
||||
if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
|
||||
if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
|
||||
if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
|
||||
if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
|
||||
if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
|
||||
if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
|
||||
if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
|
||||
if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
|
||||
if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
|
||||
if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
|
||||
if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
|
||||
if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
|
||||
if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
|
||||
if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
|
||||
if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
|
||||
if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
|
||||
if res.edx & (1 << 21): features |= CPU_FEATURE_DS
|
||||
if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
|
||||
if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
|
||||
if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
|
||||
if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
|
||||
if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
|
||||
if res.edx & (1 << 27): features |= CPU_FEATURE_SS
|
||||
if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
|
||||
if res.edx & (1 << 29): features |= CPU_FEATURE_TM
|
||||
if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
|
||||
return features
|
||||
|
||||
@c.Attribute(t.attr.packed)
|
||||
class per_cpu_data:
|
||||
user_rsp: t.CUInt64T
|
||||
kernel_rsp0: t.CUInt64T
|
||||
current_pid: t.CInt
|
||||
_pad0: t.CUInt32T
|
||||
_pad1: t.CUInt64T
|
||||
|
||||
_per_cpu: per_cpu_data
|
||||
|
||||
@t.Object
|
||||
class _CPUObject:
|
||||
tss: _tss
|
||||
features: t.CUInt32T
|
||||
def __init__(self):
|
||||
self.__init_tss__()
|
||||
|
||||
def __init_tss__(self):
|
||||
global _per_cpu
|
||||
string.memset(c.Addr(self.tss), 0, self.tss.__sizeof__())
|
||||
self.tss.io_map_base = self.tss.__sizeof__()
|
||||
string.memset(c.Addr(_per_cpu), 0, per_cpu_data.__sizeof__())
|
||||
gdt.setTSS64(5, t.CUInt64T(c.Addr(self.tss)), self.tss.__sizeof__() - 1)
|
||||
gdt.flush()
|
||||
# IA32_KERNEL_GS_BASE holds the per_cpu address for swapgs.
|
||||
# When entering from Ring 3, swapgs swaps IA32_GS_BASE (0) with
|
||||
# IA32_KERNEL_GS_BASE (_per_cpu), making gs: accessible in kernel.
|
||||
# When returning to Ring 3, swapgs swaps back, restoring GS base to 0.
|
||||
msr_write(IA32_KERNEL_GS_BASE, t.CUInt64T(c.Addr(_per_cpu)))
|
||||
|
||||
def getInfo(self, info: cpu_info | t.CPtr):
|
||||
if not info: return
|
||||
res: cpuid_result
|
||||
cpuid(0, c.Addr(res))
|
||||
(t.CUInt32T(info.vendor_id, t.CPtr))[0] = res.ebx
|
||||
(t.CUInt32T(info.vendor_id, t.CPtr))[1] = res.edx
|
||||
(t.CUInt32T(info.vendor_id, t.CPtr))[2] = res.ecx
|
||||
info.vendor_id[12] = '\0'
|
||||
info.features = self.detectFeatures()
|
||||
cpuid(1, c.Addr(res))
|
||||
info.stepping = (res.eax >> 0) & 0x0F
|
||||
info.model = (res.eax >> 4) & 0x0F
|
||||
info.family = (res.eax >> 8) & 0x0F
|
||||
info.cpu_type = (res.eax >> 12) & 0x03
|
||||
info.ext_model = (res.eax >> 16) & 0x0F
|
||||
info.ext_family = (res.eax >> 20) & 0xFF
|
||||
for i in range(4):
|
||||
cpuid(0x80000002 + i, c.Addr(res))
|
||||
base: t.CUInt32T | t.CPtr = t.CUInt32T(info.brand_string, t.CPtr)
|
||||
base[i * 4 + 0] = res.eax
|
||||
base[i * 4 + 1] = res.ebx
|
||||
base[i * 4 + 2] = res.ecx
|
||||
base[i * 4 + 3] = res.edx
|
||||
info.brand_string[47] = '\0'
|
||||
info.cpu_freq = 2000000000
|
||||
|
||||
def detectFeatures(self) -> t.CUInt32T:
|
||||
features: t.CInt32T = 0
|
||||
res: cpuid_result
|
||||
cpuid(1, c.Addr(res))
|
||||
if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
|
||||
if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
|
||||
if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
|
||||
if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
|
||||
if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
|
||||
if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
|
||||
if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
|
||||
if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
|
||||
if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
|
||||
if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
|
||||
if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
|
||||
if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
|
||||
if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
|
||||
if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
|
||||
if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
|
||||
if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
|
||||
if res.edx & (1 << 21): features |= CPU_FEATURE_DS
|
||||
if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
|
||||
if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
|
||||
if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
|
||||
if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
|
||||
if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
|
||||
if res.edx & (1 << 27): features |= CPU_FEATURE_SS
|
||||
if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
|
||||
if res.edx & (1 << 29): features |= CPU_FEATURE_TM
|
||||
if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
|
||||
return features
|
||||
|
||||
def enableInterrupts(self):
|
||||
c.Asm("sti", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
|
||||
def disableInterrupts(self):
|
||||
c.Asm("cli", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
|
||||
def enableNmis(self):
|
||||
current: t.CUInt8T = asm.inb(0x70)
|
||||
asm.outb(0x70, current & 0x7F)
|
||||
|
||||
def disableNmis(self):
|
||||
current: t.CUInt8T = asm.inb(0x70)
|
||||
asm.outb(0x70, current | 0x80)
|
||||
|
||||
def readCR0(self) -> t.CUInt64T:
|
||||
cr0: t.CUInt64T
|
||||
c.Asm(f"""mov rax, cr0
|
||||
mov {c.AsmOut(cr0, t.ASM_DESCR.OUTPUT_REG)}, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
return cr0
|
||||
|
||||
def writeCR0(self, value: t.CUInt64T):
|
||||
c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
|
||||
mov cr0, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
|
||||
def readCR3(self) -> t.CUInt64T:
|
||||
cr3: t.CUInt64T
|
||||
c.Asm(f"""mov rax, cr3
|
||||
mov {c.AsmOut(cr3, t.ASM_DESCR.OUTPUT_REG)}, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
return cr3
|
||||
|
||||
def writeCR3(self, value: t.CUInt64T):
|
||||
c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
|
||||
mov cr3, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
|
||||
def readCR4(self) -> t.CUInt64T:
|
||||
cr4: t.CUInt64T
|
||||
c.Asm(f"""mov rax, cr4
|
||||
mov {c.AsmOut(cr4, t.ASM_DESCR.OUTPUT_REG)}, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
return cr4
|
||||
|
||||
def writeCR4(self, value: t.CUInt64T):
|
||||
c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
|
||||
mov cr4, rax""",
|
||||
[t.ASM_DESCR.CLOBBER_RAX])
|
||||
|
||||
def readMSR(self, msr: t.CUInt32T) -> t.CUInt64T:
|
||||
return msr_read(msr)
|
||||
|
||||
def writeMSR(self, msr: t.CUInt32T, value: t.CUInt64T):
|
||||
msr_write(msr, value)
|
||||
|
||||
def setTSSRSP0(self, rsp0: t.CUInt64T):
|
||||
global _per_cpu
|
||||
self.tss.rsp0 = rsp0
|
||||
_per_cpu.kernel_rsp0 = rsp0
|
||||
|
||||
def set_kernel_rsp0(rsp0: t.CUInt64T):
|
||||
global _per_cpu
|
||||
_per_cpu.kernel_rsp0 = rsp0
|
||||
50
VKernel/Kernel/drivers/core/cpu/fpu.py
Normal file
50
VKernel/Kernel/drivers/core/cpu/fpu.py
Normal file
@@ -0,0 +1,50 @@
|
||||
import cpu
|
||||
import t, c
|
||||
|
||||
|
||||
# FPU上下文结构体
|
||||
@c.Attribute(t.attr.aligned(16))
|
||||
class fpu_context:
|
||||
data: t.CUInt8T[512] # FXSAVE区域大小
|
||||
|
||||
|
||||
@t.Object
|
||||
class _FPUObject:
|
||||
CPUObject: cpu._CPUObject | t.CPtr
|
||||
# 初始化FPU
|
||||
def __init__(self, CPUObject: cpu._CPUObject | t.CPtr):
|
||||
self.enable()
|
||||
self.CPUObject = CPUObject
|
||||
c.Asm("fninit", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
# 启用FPU
|
||||
def enable(self):
|
||||
cr0: t.CUInt64T = self.CPUObject.readCR0()
|
||||
# 清除EM位（禁用仿真），设置MP位（监控协处理器）
|
||||
cr0 &= ~(1 << 2); # 清除EM位
|
||||
cr0 |= (1 << 1); # 设置MP位
|
||||
# 写入CR0寄存器
|
||||
self.CPUObject.writeCR0(cr0)
|
||||
# 读取CR4寄存器
|
||||
cr4: t.CUInt64T = self.CPUObject.readCR4()
|
||||
# 设置OSFXSR位和OSXMMEXCPT位，启用SSE
|
||||
cr4 |= (1 << 9) | (1 << 10)
|
||||
# 写入CR4寄存器
|
||||
self.CPUObject.writeCR4(cr4)
|
||||
# 初始化FPU
|
||||
c.Asm("fninit", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
# 禁用FPU
|
||||
def disable(self):
|
||||
cr0: t.CUInt64T = self.CPUObject.readCR0()
|
||||
# 设置EM位（启用仿真），清除MP位（禁用监控协处理器）
|
||||
cr0 |= (1 << 2) # 设置EM位
|
||||
cr0 &= ~(1 << 1) # 清除MP位
|
||||
# 写入CR0寄存器
|
||||
self.CPUObject.writeCR0(cr0)
|
||||
# 保存FPU上下文
|
||||
def save_context(self, context: fpu_context | t.CPtr):
|
||||
# 保存FPU状态到内存
|
||||
c.Asm(f"fxsave [{c.AsmInp(context, t.ASM_DESCR.REG_ANY)}]", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
# 恢复FPU上下文
|
||||
def restore_context(self, context: t.CConst | fpu_context | t.CPtr):
|
||||
# 从内存恢复FPU状态
|
||||
c.Asm(f"fxrstor [{c.AsmInp(context, t.ASM_DESCR.REG_ANY)}]", [t.ASM_DESCR.CLOBBER_MEMORY])
|
||||
Reference in New Issue
Block a user