fix(gen): zip/enumerate 的 range 源工作位宽随参数（仿 for-range），修 range(3) 被 i64 索引误判窄化
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@@ -1325,6 +1325,22 @@ novirtual class StmtGenCifMixin:
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return GenTypes.SEQ_KIND_STR
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return 0
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# _range_work_bits - range 工作位宽：取各已求值参数位宽的最大值，下限 i32（32）。
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# 与 `for i in range(...)` 的 loop_store_ty 同口径，避免内部 i64 索引写回 i32 循环变量时误报窄化。
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def _range_work_bits(self, a: mlirlite.Value*, b: mlirlite.Value*, c: mlirlite.Value*) -> int:
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"""Working integer width for a range() source: max of the provided argument widths, at least 32."""
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bits: int = 32
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if a is not None and a.Ty is not None:
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ab: int = self.Gen.ExprGenBase.get_llvm_type_bits(a.Ty)
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if ab > bits: bits = ab
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if b is not None and b.Ty is not None:
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bb: int = self.Gen.ExprGenBase.get_llvm_type_bits(b.Ty)
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if bb > bits: bits = bb
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if c is not None and c.Ty is not None:
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cb: int = self.Gen.ExprGenBase.get_llvm_type_bits(c.Ty)
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if cb > bits: bits = cb
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return bits
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def _build_seq_loop(self, trans: HT.Translator*, for_node: ast.For*, t1: str, t2: str, src1: ast.AST*, src2: ast.AST*, n_srcs: int) -> int:
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"""Build a sequence iteration loop for enumerate (n_srcs=1) or zip (n_srcs=2)."""
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pool: memhub.MemBuddy* = trans.Pool
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@@ -1347,34 +1363,45 @@ novirtual class StmtGenCifMixin:
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l1_data: mlirlite.Value* = None
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l1_esize: mlirlite.Value* = None
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elem1_ty: mlirlite.LLVMType* = i8_ptr_ty
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# range 的工作位宽/类型（随参数位宽，仿 `for i in range(...)`）；非 range 源不使用。
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r1_wty: mlirlite.LLVMType* = None
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r1_bits: int = 0
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if kind1 == GenTypes.SEQ_KIND_RANGE:
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elem1_ty = i32_ty
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r1_start = mlirlite.const_int64(pool, 0)
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r1_step = mlirlite.const_int64(pool, 1)
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r1_stop = mlirlite.const_int64(pool, 0)
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# assign to a temp before taking args (chained cast attrs misinfer field offsets)
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# 先求值参数，再由参数位宽决定工作类型：i32 字面量就按 i32 算，
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# 避免内部 i64 索引写回 i32 循环变量时触发隐式窄化误报。
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call_src1: ast.Call* = ast.Call*(src1)
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cargs1: list[ast.AST*]* = call_src1.args
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a1: mlirlite.Value* = None
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b1: mlirlite.Value* = None
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c1: mlirlite.Value* = None
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n1: sizet = 0
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if cargs1 is not None:
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n1: sizet = len(cargs1)
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n1 = len(cargs1)
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if n1 >= 1:
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sv: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(0), trans._funcs, trans._func_count, trans)
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if sv is None:
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a1 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(0), trans._funcs, trans._func_count, trans)
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if a1 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs1.get(0), "failed to translate the range argument", "TypeError")
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r1_stop = self.Gen.ExprGenBase.coerce_to_type(builder, sv, i64_ty, cargs1.get(0))
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if n1 >= 2:
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sv2: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(1), trans._funcs, trans._func_count, trans)
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if sv2 is None:
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b1 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(1), trans._funcs, trans._func_count, trans)
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if b1 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs1.get(1), "failed to translate the range argument", "TypeError")
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r1_start = self.Gen.ExprGenBase.coerce_to_type(builder, sv2, i64_ty, cargs1.get(1))
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if n1 >= 3:
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sv3: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(2), trans._funcs, trans._func_count, trans)
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if sv3 is None:
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c1 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs1.get(2), trans._funcs, trans._func_count, trans)
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if c1 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs1.get(2), "failed to translate the range argument", "TypeError")
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r1_step = self.Gen.ExprGenBase.coerce_to_type(builder, sv3, i64_ty, cargs1.get(2))
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r1_bits = self._range_work_bits(a1, b1, c1)
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r1_wty = self.Gen.ExprGenBase._int_type_of_bits(pool, r1_bits)
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if r1_wty is None: r1_wty = i32_ty
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elem1_ty = r1_wty
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r1_start = mlirlite.const_int(pool, r1_bits, 0)
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r1_step = mlirlite.const_int(pool, r1_bits, 1)
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r1_stop = mlirlite.const_int(pool, r1_bits, 0)
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if a1 is not None: r1_stop = self.Gen.ExprGenBase.coerce_to_type(builder, a1, r1_wty, cargs1.get(0))
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if b1 is not None: r1_start = self.Gen.ExprGenBase.coerce_to_type(builder, b1, r1_wty, cargs1.get(1))
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if c1 is not None: r1_step = self.Gen.ExprGenBase.coerce_to_type(builder, c1, r1_wty, cargs1.get(2))
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elif kind1 == GenTypes.SEQ_KIND_STR:
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elem1_ty = i8_ty
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s1_ptr = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, src1, trans._funcs, trans._func_count, trans)
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@@ -1397,37 +1424,47 @@ novirtual class StmtGenCifMixin:
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r2_start: mlirlite.Value* = None
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r2_stop: mlirlite.Value* = None
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r2_step: mlirlite.Value* = None
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# range 的工作位宽/类型（source 2 对称处理）。
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r2_wty: mlirlite.LLVMType* = None
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r2_bits: int = 0
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if n_srcs >= 2:
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kind2 = self._seq_kind(trans, src2)
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if kind2 == 0: self.Gen.TypeGenErr.fatal_error(for_node, "sequence iteration: source 2 type is not supported")
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if kind2 == GenTypes.SEQ_KIND_RANGE:
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elem2_ty = i32_ty
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r2_start = mlirlite.const_int64(pool, 0)
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r2_step = mlirlite.const_int64(pool, 1)
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r2_stop = mlirlite.const_int64(pool, 0)
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# assign to a temp before taking args (chained cast attrs misinfer field offsets)
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# 与 source 1 同口径：工作类型随参数位宽，避免 i64 索引写回窄位宽循环变量误报。
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call_src2: ast.Call* = ast.Call*(src2)
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cargs2: list[ast.AST*]* = call_src2.args
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a2: mlirlite.Value* = None
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b2: mlirlite.Value* = None
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c2: mlirlite.Value* = None
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n2: sizet = 0
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if cargs2 is not None:
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n2: sizet = len(cargs2)
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n2 = len(cargs2)
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if n2 >= 1:
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svz: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(0), trans._funcs, trans._func_count, trans)
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if svz is None:
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a2 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(0), trans._funcs, trans._func_count, trans)
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if a2 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs2.get(0), "failed to translate the range argument", "TypeError")
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r2_stop = self.Gen.ExprGenBase.coerce_to_type(builder, svz, i64_ty, cargs2.get(0))
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if n2 >= 2:
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svz2: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(1), trans._funcs, trans._func_count, trans)
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if svz2 is None:
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b2 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(1), trans._funcs, trans._func_count, trans)
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if b2 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs2.get(1), "failed to translate the range argument", "TypeError")
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r2_start = self.Gen.ExprGenBase.coerce_to_type(builder, svz2, i64_ty, cargs2.get(1))
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if n2 >= 3:
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svz3: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(2), trans._funcs, trans._func_count, trans)
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if svz3 is None:
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c2 = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, cargs2.get(2), trans._funcs, trans._func_count, trans)
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if c2 is None:
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# fail-fast: range argument failed to translate
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self.Gen.TypeGenErr.fatal_error(cargs2.get(2), "failed to translate the range argument", "TypeError")
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r2_step = self.Gen.ExprGenBase.coerce_to_type(builder, svz3, i64_ty, cargs2.get(2))
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r2_bits = self._range_work_bits(a2, b2, c2)
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r2_wty = self.Gen.ExprGenBase._int_type_of_bits(pool, r2_bits)
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if r2_wty is None: r2_wty = i32_ty
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elem2_ty = r2_wty
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r2_start = mlirlite.const_int(pool, r2_bits, 0)
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r2_step = mlirlite.const_int(pool, r2_bits, 1)
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r2_stop = mlirlite.const_int(pool, r2_bits, 0)
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if a2 is not None: r2_stop = self.Gen.ExprGenBase.coerce_to_type(builder, a2, r2_wty, cargs2.get(0))
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if b2 is not None: r2_start = self.Gen.ExprGenBase.coerce_to_type(builder, b2, r2_wty, cargs2.get(1))
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if c2 is not None: r2_step = self.Gen.ExprGenBase.coerce_to_type(builder, c2, r2_wty, cargs2.get(2))
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elif kind2 == GenTypes.SEQ_KIND_STR:
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elem2_ty = i8_ty
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s2_ptr = self.Gen.ExprGen.translate_value(builder, pool, trans.Module, src2, trans._funcs, trans._func_count, trans)
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@@ -1487,7 +1524,11 @@ novirtual class StmtGenCifMixin:
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mlirlite.position_at_end(builder, cond_bb)
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cur_idx: mlirlite.Value* = mlirlite.build_load(builder, i64_ty, idx_alloca)
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done1: mlirlite.Value* = None
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if kind1 == GenTypes.SEQ_KIND_RANGE: done1 = mlirlite.build_icmp(builder, mlirlite.ICMP_SLT, cur_idx, r1_stop)
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if kind1 == GenTypes.SEQ_KIND_RANGE:
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# range 的索引按工作位宽截断后再比较（索引是编译器内部量，不涉及用户窄化）
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idx1_cmp: mlirlite.Value* = cur_idx
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if r1_bits != 64: idx1_cmp = mlirlite.build_trunc(builder, cur_idx, r1_wty)
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done1 = mlirlite.build_icmp(builder, mlirlite.ICMP_SLT, idx1_cmp, r1_stop)
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elif kind1 == GenTypes.SEQ_KIND_STR:
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ch_ptr1: mlirlite.Value* = mlirlite.build_gep(builder, i8_ty, s1_ptr, cur_idx)
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ch1: mlirlite.Value* = mlirlite.build_load(builder, i8_ty, ch_ptr1)
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@@ -1497,7 +1538,10 @@ novirtual class StmtGenCifMixin:
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cont: mlirlite.Value* = done1
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if n_srcs >= 2:
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done2: mlirlite.Value* = None
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if kind2 == GenTypes.SEQ_KIND_RANGE: done2 = mlirlite.build_icmp(builder, mlirlite.ICMP_SLT, cur_idx, r2_stop)
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if kind2 == GenTypes.SEQ_KIND_RANGE:
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idx2_cmp: mlirlite.Value* = cur_idx
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if r2_bits != 64: idx2_cmp = mlirlite.build_trunc(builder, cur_idx, r2_wty)
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done2 = mlirlite.build_icmp(builder, mlirlite.ICMP_SLT, idx2_cmp, r2_stop)
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elif kind2 == GenTypes.SEQ_KIND_STR:
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ch_ptr2: mlirlite.Value* = mlirlite.build_gep(builder, i8_ty, s2_ptr, cur_idx)
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ch2: mlirlite.Value* = mlirlite.build_load(builder, i8_ty, ch_ptr2)
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@@ -1512,7 +1556,9 @@ novirtual class StmtGenCifMixin:
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# source-1 element
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v1: mlirlite.Value* = None
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if kind1 == GenTypes.SEQ_KIND_RANGE:
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step1: mlirlite.Value* = mlirlite.build_mul(builder, cur_idx, r1_step)
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idx1_b: mlirlite.Value* = cur_idx
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if r1_bits != 64: idx1_b = mlirlite.build_trunc(builder, cur_idx, r1_wty)
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step1: mlirlite.Value* = mlirlite.build_mul(builder, idx1_b, r1_step)
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v1 = mlirlite.build_add(builder, r1_start, step1)
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elif kind1 == GenTypes.SEQ_KIND_STR:
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ch_ptr1b: mlirlite.Value* = mlirlite.build_gep(builder, i8_ty, s1_ptr, cur_idx)
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@@ -1539,7 +1585,9 @@ novirtual class StmtGenCifMixin:
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# source-2 element → t2
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v2: mlirlite.Value* = None
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if kind2 == GenTypes.SEQ_KIND_RANGE:
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step2: mlirlite.Value* = mlirlite.build_mul(builder, cur_idx, r2_step)
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idx2_b: mlirlite.Value* = cur_idx
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if r2_bits != 64: idx2_b = mlirlite.build_trunc(builder, cur_idx, r2_wty)
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step2: mlirlite.Value* = mlirlite.build_mul(builder, idx2_b, r2_step)
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v2 = mlirlite.build_add(builder, r2_start, step2)
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elif kind2 == GenTypes.SEQ_KIND_STR:
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ch_ptr2b: mlirlite.Value* = mlirlite.build_gep(builder, i8_ty, s2_ptr, cur_idx)
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