feat(gen): 字节序 bswap 改为按目标端序判断（BigEndian/LittleEndian 都相对目标），原语改名 apply_byte_order_bswap
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@@ -1429,7 +1429,7 @@ novirtual class AssignGenMixin:
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store_val: mlirlite.Value* = elem_val
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if elem_ptr.Ty is not None and elem_ptr.Ty.Pointee != 0: store_val = self.Gen.ExprGenBase.coerce_to_type(builder, elem_val, elem_ptr.Ty.Pointee, elem_node)
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# BigEndian array: store each element byte-swapped (pairs the un-swap on element read).
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store_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, store_val, byte_order)
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store_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, store_val, byte_order)
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mlirlite.build_store(builder, store_val, elem_ptr)
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return 0
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@@ -1588,7 +1588,7 @@ novirtual class AssignGenMixin:
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if cur_val is None:
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# fail-fast: attribute current value load failed
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self.Gen.TypeGenErr.fatal_error(target, "cannot load the current value of the attribute", "TypeError")
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cur_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, cur_val, bo_fa)
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cur_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, cur_val, bo_fa)
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# 3. Translate the RHS value
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rhs_val: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, mod, aug.value, None, 0, trans)
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@@ -1609,7 +1609,7 @@ novirtual class AssignGenMixin:
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self.Gen.TypeGenErr.fatal_error(target, "type coercion failed", "TypeError")
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# BigEndian field: re-swap the result so the slot keeps the byte-swapped pattern
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# (pairs the un-swap of cur_val above, keeping memory big-endian).
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result = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, result, bo_fa)
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result = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, result, bo_fa)
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mlirlite.build_store(builder, result, field_ptr, vol_fa)
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return 0
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@@ -1661,7 +1661,7 @@ novirtual class AssignGenMixin:
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if cur_val is None:
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# fail-fast: element current value load failed
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self.Gen.TypeGenErr.fatal_error(target, "cannot load the current value of the subscript element", "TypeError")
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cur_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, cur_val, bo_sa)
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cur_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, cur_val, bo_sa)
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# 3. Translate the RHS value
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rhs_val: mlirlite.Value* = self.Gen.ExprGen.translate_value(builder, pool, mod, aug.value, None, 0, trans)
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@@ -1681,7 +1681,7 @@ novirtual class AssignGenMixin:
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# fail-fast: type coercion failed
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self.Gen.TypeGenErr.fatal_error(target, "type coercion failed", "TypeError")
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# BigEndian array element: re-swap the result so the slot stays byte-swapped (pairs cur_val above).
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result = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, result, bo_sa)
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result = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, result, bo_sa)
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mlirlite.build_store(builder, result, elem_ptr, vol_sa)
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return 0
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@@ -1770,7 +1770,7 @@ novirtual class AssignGenMixin:
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target_ty = target_alloca.Ty.Pointee
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cur_val = mlirlite.build_load(builder, target_ty, target_alloca, vol_aa)
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# BigEndian local: un-swap the loaded slot value before the arithmetic (paired with the store below).
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cur_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, cur_val, bo_aa)
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cur_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, cur_val, bo_aa)
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if cur_val is None:
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# fail-fast: target variable current value load failed
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@@ -1838,7 +1838,7 @@ novirtual class AssignGenMixin:
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# Ordinary local variable
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if target_alloca is not None:
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# BigEndian local: re-swap the result so the slot keeps the byte-swapped pattern (pairs the load above).
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result = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, result, bo_aa)
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result = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, result, bo_aa)
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mlirlite.build_store(builder, result, target_alloca, vol_aa)
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return 0
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@@ -2466,7 +2466,7 @@ novirtual class AssignGenMixin:
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# BigEndian local: store the byte-swapped value so the slot is big-endian in memory
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# (pairs the un-swap done by ExprGenName.translate_name_value on the read path).
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decl_bo: int = self.Gen.VarGen.var_byte_order(self.Gen.VarGen.lookup_var_entry(trans.SymTab, nm.id))
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rhs_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, rhs_val, decl_bo)
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rhs_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, rhs_val, decl_bo)
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mlirlite.build_store(builder, rhs_val, alloca, vol_laa)
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# P2 willFree：带注解声明/赋值后清除失效态（新变量本就为 0；复用槽兜底）
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self.Gen.VarGen.clear_var_freed(trans.SymTab, nm.id)
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@@ -2569,7 +2569,7 @@ novirtual class AssignGenMixin:
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if sub_lv_b.value is not None and sub_lv_b.value.kind() == ast.ASTKind.Name:
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sub_nm_lv: ast.Name* = ast.Name*(sub_lv_b.value)
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if sub_nm_lv.id is not None: bo_lv = self.Gen.VarGen.var_byte_order(self.Gen.VarGen.lookup_var_entry(trans.SymTab, sub_nm_lv.id))
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store_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, store_val, bo_lv)
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store_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, store_val, bo_lv)
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# t.CVolatile 字段 / rawptr[t.CVolatile|T] 基址：写出同样带 volatile。
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vol_lv: int = 0
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if is_attr != 0:
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@@ -2794,7 +2794,7 @@ novirtual class AssignGenMixin:
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if sub_wr is not None and sub_wr.value is not None and sub_wr.value.kind() == ast.ASTKind.Name:
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sub_nm_sw: ast.Name* = ast.Name*(sub_wr.value)
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if sub_nm_sw.id is not None: bo_sw = self.Gen.VarGen.var_byte_order(self.Gen.VarGen.lookup_var_entry(trans.SymTab, sub_nm_sw.id))
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store_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, store_val, bo_sw)
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store_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, store_val, bo_sw)
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# rawptr[t.CVolatile|T] base: p[i] = v stores with volatile when the base is resolvable
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vol_sw: int = 0
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if sub_wr is not None: vol_sw = self.Gen.ExprGenAttr.base_pointee_is_volatile(pool, trans, sub_wr.value)
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@@ -2932,7 +2932,7 @@ novirtual class AssignGenMixin:
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# BigEndian field: store the byte-swapped value so the slot is big-endian in memory
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# (pairs the un-swap done by ExprGenAttr.translate_attribute on the load path).
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bo_fw: int = self.Gen.ExprGenAttr.attr_field_byte_order(pool, trans, target)
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store_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, store_val, bo_fw)
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store_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, store_val, bo_fw)
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# t.CVolatile field: store with the volatile qualifier
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vol_fw: int = self.Gen.ExprGenAttr.attr_field_is_volatile(pool, trans, target)
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# rawptr[t.CVolatile|T] base: p.field = v also stores with volatile
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@@ -3045,7 +3045,7 @@ novirtual class AssignGenMixin:
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# BigEndian local variable: store the byte-swapped value so the slot is big-endian in
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# memory (pairs the un-swap done by ExprGenName.translate_name_value on the read path).
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bo_las: int = self.Gen.VarGen.var_byte_order(self.Gen.VarGen.lookup_var_entry(trans.SymTab, nm.id))
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store_val = self.Gen.ExprGenBase.apply_bswap_if_big(pool, builder, store_val, bo_las)
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store_val = self.Gen.ExprGenBase.apply_byte_order_bswap(pool, builder, store_val, bo_las)
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# t.CVolatile local variable: store with the volatile qualifier
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vol_las: int = self.Gen.VarGen.var_is_volatile(self.Gen.VarGen.lookup_var_entry(trans.SymTab, nm.id))
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# M3 所有权记账：必须先记账再写值（覆盖释放要读到旧值）；
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@@ -651,10 +651,10 @@ novirtual class ExprGenAttr(ExprGenBase.ExprGenBase):
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if cast_ptr_rn is not None:
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rn_alias_val: mlirlite.Value* = mlirlite.build_load(builder, decl_ty_rn, cast_ptr_rn)
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# BigEndian REnum payload alias: un-swap the load (pairing the write side).
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return self.apply_bswap_if_big(pool, builder, rn_alias_val, alias_fe.ByteOrder)
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return self.apply_byte_order_bswap(pool, builder, rn_alias_val, alias_fe.ByteOrder)
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rn_slot_val: mlirlite.Value* = mlirlite.build_load(builder, alias_fe.Ty, alias_ptr, vol_ba_rd)
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# BigEndian REnum slot: un-swap the load (pairing the write side).
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return self.apply_bswap_if_big(pool, builder, rn_slot_val, alias_fe.ByteOrder)
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return self.apply_byte_order_bswap(pool, builder, rn_slot_val, alias_fe.ByteOrder)
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# property getter fallback: when obj.attr is a @property/@x.getter method, emit a call
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# (try before reporting a field-not-found error, to avoid a misleading message)
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if field_info is None and at.value is not None and trans is not None:
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@@ -717,7 +717,7 @@ novirtual class ExprGenAttr(ExprGenBase.ExprGenBase):
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if casted is not None:
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union_val_rd: mlirlite.Value* = mlirlite.build_load(builder, field_ty, casted, field_vol_rd)
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# BigEndian field: the slot holds the byte-swapped pattern, so un-swap the load.
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return self.apply_bswap_if_big(pool, builder, union_val_rd, field_info.ByteOrder)
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return self.apply_byte_order_bswap(pool, builder, union_val_rd, field_info.ByteOrder)
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return None
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# normal struct: GEP + load
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field_idx: int = field_info.Index
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@@ -735,14 +735,14 @@ novirtual class ExprGenAttr(ExprGenBase.ExprGenBase):
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if cast_ptr_rd is not None:
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rn_val_rd: mlirlite.Value* = mlirlite.build_load(builder, decl_ty_rd, cast_ptr_rd, field_vol_rd)
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# BigEndian REnum payload slot: un-swap the load, pairing with the write side.
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return self.apply_bswap_if_big(pool, builder, rn_val_rd, field_info.ByteOrder)
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return self.apply_byte_order_bswap(pool, builder, rn_val_rd, field_info.ByteOrder)
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# an array-typed field cannot be loaded as an SSA value; return the field pointer for
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# later indexing: self.state[0] → GEP the state field → GEP the array element
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if self.is_array_type(field_ty) != 0: return field_ptr
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loaded_val: mlirlite.Value* = mlirlite.build_load(builder, field_ty, field_ptr, field_vol_rd)
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# BigEndian field: the memory slot holds the byte-swapped pattern, so un-swap the
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# loaded value; a no-op for non-16/32/64-bit ints (pointers/aggregates unaffected).
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loaded_val = self.apply_bswap_if_big(pool, builder, loaded_val, field_info.ByteOrder)
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loaded_val = self.apply_byte_order_bswap(pool, builder, loaded_val, field_info.ByteOrder)
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# a union-typed field (e.g. Token*) is compiled as i8*; when AnnotClassName points to a
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# concrete struct type, bitcast the loaded pointer (value→pointer bitcast would be invalid).
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fc_annot: str = self.Gen.StructGen.get_field_annot_class_name(field_info)
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@@ -149,20 +149,26 @@ novirtual class ExprGenBase:
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string.memset(ty, 0, mlirlite.LLVMType.__sizeof__())
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*ty = *mlirlite.LLVMType.Int(bits)
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return ty
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# apply_bswap_if_big - byte-order bswap primitive (TPC parity: BaseGen._apply_bswap_if_big).
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# Only BigEndian (byte_order==1) on a 16/32/64-bit integer emits `llvm.bswap`; every other case
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# returns val unchanged. byte_order==0 (native) must be zero-cost: no IR is emitted at all, and
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# 2 (LittleEndian) also returns unchanged because the host is little-endian (same as TPC, which
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# only swaps for 'big'), so the in-memory slot stays little-endian and no swap is needed.
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# apply_byte_order_bswap - byte-order bswap primitive (TPC parity: BaseGen._apply_bswap_if_big,
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# extended to judge BOTH markers against the target's native order).
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# Swapping is needed only when the declared encoding differs from the target's native order,
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# so: BigEndian field on a little-endian target -> swap; LittleEndian field on a big-endian
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# target -> swap; declared order == target order -> no swap. byte_order==0 (unspecified)
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# means native and is always zero-cost: no IR is emitted at all. 16/32/64-bit integers only,
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# matching TPC (i8/floats/pointers/aggregates are never swapped).
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# Call name: bare "llvm.bswap" (no width suffix). build_call emits `call i32 @llvm.bswap(i32 %x)`;
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# __function.vp:2607 detects a bare `@llvm.*` (non-`llvm.mlir.`) callee and renders it as
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# `llvm.call_intrinsic "llvm.bswap"(...)`, and mlir-translate mangles the name from the operand
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# type to `llvm.bswap.i32` (README.md:367-378, the same path used by CallGenVa.vp:123 `llvm.va_start`
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# -> `llvm.va_start.p0`). Passing `llvm.bswap.i32` explicitly is unnecessary and would break the
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# uniform mangle path, so the un-suffixed name is used.
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def apply_bswap_if_big(self, pool: memhub.MemBuddy*, builder: mlirlite.IRBuilder*, val: mlirlite.Value*, byte_order: int) -> mlirlite.Value*:
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"""Return llvm.bswap(val) when byte_order==1 and val is a 16/32/64-bit int; else val unchanged."""
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if byte_order != 1: return val
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def apply_byte_order_bswap(self, pool: memhub.MemBuddy*, builder: mlirlite.IRBuilder*, val: mlirlite.Value*, byte_order: int) -> mlirlite.Value*:
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"""Return llvm.bswap(val) when val's declared byte_order differs from the target order; else val."""
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if byte_order == 0: return val
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# 1=BigEndian, 2=LittleEndian; compare against the target's native order.
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want_big: int = 0
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if byte_order == 1: want_big = 1
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if want_big == self.Gen.TypeGenResolve.target_is_big_endian(): return val
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if val is None or val.Ty is None: return val
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bits: int = self.get_llvm_type_bits(val.Ty)
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if bits != 16 and bits != 32 and bits != 64: return val
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@@ -180,7 +180,7 @@ novirtual class ExprGenName(ExprGenBase.ExprGenBase):
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bo_l = self.Gen.VarGen.var_byte_order(ve_l)
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local_val_l: mlirlite.Value* = mlirlite.build_load(builder, load_ty, alloca, vol_l)
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# BigEndian local: the slot is byte-swapped, so un-swap the load (pairs the store in AssignGenMixin).
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return self.apply_bswap_if_big(pool, builder, local_val_l, bo_l)
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return self.apply_byte_order_bswap(pool, builder, local_val_l, bo_l)
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# REPL session variables: a name missing from the local table is read back from its ctx slot,
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# checked after locals and before module aliases; non-REPL behavior is unchanged.
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@@ -571,7 +571,7 @@ novirtual class ExprGenName(ExprGenBase.ExprGenBase):
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# on load (pairs the element store in AssignGenMixin). Non-Name bases are
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# not covered (matches TPC, which also keys off the base Name).
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bo_arr_rd: int = self.Gen.VarGen.var_byte_order(self.Gen.VarGen.lookup_var_entry(trans.SymTab, nm.id))
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return self.apply_bswap_if_big(pool, builder, arr_val_rd, bo_arr_rd)
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return self.apply_byte_order_bswap(pool, builder, arr_val_rd, bo_arr_rd)
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return None
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case mlirlite.LLVMType.Struct(_fs_v, _fc_v, lsn_v):
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# list[T] value variable (an unannotated assignment rhs returns a list
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@@ -1495,6 +1495,24 @@ novirtual class TypeGenResolve(TypeGenBase.TypeGenBase):
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if self._is_t_attr(node, "BigEndian", imported_modules) != 0: return 1
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if self._is_t_attr(node, "LittleEndian", imported_modules) != 0: return 2
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return 0
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def target_is_big_endian(self) -> int:
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"""Whether the compilation target is big-endian (1) or little-endian (0).
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The configured data layout wins: LLVM's first data-layout field is the endianness
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marker ('e' = little, 'E' = big; omitted means little). Without a data layout, fall
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back to the triple's `_be` arch suffix (e.g. aarch64_be-...); otherwise little, which
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is the default target. Both byte-order markers are judged against this: a `t.BigEndian`
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field on a big-endian target needs no swap, and a `t.LittleEndian` field on a
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big-endian target does."""
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dl: str = Config.TargetDataLayout
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if dl is not None and dl[0] != '\0':
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if dl[0] == 'E': return 1
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if dl[0] == 'e': return 0
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tr: str = Config.TargetTriple
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if tr is not None:
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ei: int = 0
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while tr[ei] != '\0' and tr[ei] != '-': ei += 1
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if ei >= 3 and tr[ei - 3] == '_' and tr[ei - 2] == 'b' and tr[ei - 1] == 'e': return 1
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return 0
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def _ref_marker_name_mode(self, node: ast.AST*) -> int:
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"""Syntactic value-reference marker test (no import context): 0=none / 1=CRef / 2=CTempRef."""
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if node is None: return 0
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