TermiNexus
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内容由用户产出，本次仅代为提交、未做任何语义修改；含 static 修饰符前置迁移等（新增 static 前缀 16 行）。提交消息为中性描述——如需更精确的说明请 amend。
376 lines
14 KiB
Plaintext
376 lines
14 KiB
Plaintext
import intr.gdt as gdt
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import string
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import asm
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define IA32_KERNEL_GS_BASE = 0xC0000102
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define KERN_STACK_SIZE = 8192
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define CPU_FEATURE_FPU = (1 << 0)
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define CPU_FEATURE_PSE = (1 << 1)
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define CPU_FEATURE_MSR = (1 << 2)
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define CPU_FEATURE_PAE = (1 << 3)
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define CPU_FEATURE_MCE = (1 << 4)
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define CPU_FEATURE_CX8 = (1 << 5)
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define CPU_FEATURE_APIC = (1 << 6)
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define CPU_FEATURE_SEP = (1 << 7)
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define CPU_FEATURE_MTRR = (1 << 8)
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define CPU_FEATURE_PGE = (1 << 9)
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define CPU_FEATURE_MCA = (1 << 10)
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define CPU_FEATURE_CMOV = (1 << 11)
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define CPU_FEATURE_PAT = (1 << 12)
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define CPU_FEATURE_PSE36 = (1 << 13)
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define CPU_FEATURE_PSN = (1 << 14)
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define CPU_FEATURE_CLFSH = (1 << 15)
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define CPU_FEATURE_DS = (1 << 16)
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define CPU_FEATURE_ACPI = (1 << 17)
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define CPU_FEATURE_MMX = (1 << 18)
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define CPU_FEATURE_FXSR = (1 << 19)
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define CPU_FEATURE_SSE = (1 << 20)
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define CPU_FEATURE_SSE2 = (1 << 21)
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define CPU_FEATURE_SS = (1 << 22)
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define CPU_FEATURE_HTT = (1 << 23)
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define CPU_FEATURE_TM = (1 << 24)
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define CPU_FEATURE_PBE = (1 << 25)
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class cpu_info:
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vendor_id: [13]char
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brand_string: [48]char
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features: uint32
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family: uint32
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model: uint32
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stepping: uint32
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cpu_type: uint32
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ext_model: uint32
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ext_family: uint32
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cpu_freq: uint64
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@__attribute__(packed)
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class _tss:
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# x86_64 TSS 布局：偏移 0 为 4 字节保留字段（对齐 gdt.vp:32 的
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# "reserved0(4) rsp0(8) ..." 与 tss_buf: t.CArray[uint8, 104]）。
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# 此前写作 uint64 使 RSP0 落在偏移 8、结构体 108B —— 与硬件 104B 布局
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# 及 gdt 的 tss_buf(104B) 不一致（N6）。
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reserved0: uint32
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rsp0: uint64
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rsp1: uint64
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rsp2: uint64
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reserved1: uint64
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ist1: uint64
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ist2: uint64
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ist3: uint64
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ist4: uint64
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ist5: uint64
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ist6: uint64
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ist7: uint64
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reserved2: uint64
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reserved3: uint16
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io_map_base: uint16
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class cpuid_result:
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eax: uint32
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ebx: uint32
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ecx: uint32
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edx: uint32
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@__attribute__(packed)
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def _rdmsr_naked():
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__asm__(f"""rdmsr
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shl rdx, 32
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or rax, rdx
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ret""",
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op=[ASM_DESCR.CLOBBER_RDX])
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@__attribute__(packed)
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def _wrmsr_naked():
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# msr_write sets ecx=msr, r8=value. wrmsr needs ECX=msr, EDX:EAX=value.
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# Old code did `mov rax,rcx` (rax=msr) which wrote (value>>32):msr to MSR,
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# corrupting IA32_KERNEL_GS_BASE -> swapgs -> #GP on gs:[0]. Fixed below.
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__asm__(f"""mov rax, r8
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mov rdx, r8
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shr rdx, 32
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wrmsr
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ret""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RDX])
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def msr_read(msr: uint32) -> uint64:
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result: uint64 = 0
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func: callable = _rdmsr_naked
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__asm__(f"""mov ecx, {asminp(msr, ASM_DESCR.REG_ANY)}
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call {asminp(func, ASM_DESCR.REG_ANY)}
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mov {asmout(result, ASM_DESCR.OUTPUT_REG)}, rax""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX, ASM_DESCR.CLOBBER_RDX])
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return result
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def msr_write(msr: uint32, value: uint64):
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func: callable = _wrmsr_naked
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__asm__(f"""mov ecx, {asminp(msr, ASM_DESCR.REG_ANY)}
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mov r8, {asminp(value, ASM_DESCR.REG_ANY)}
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call {asminp(func, ASM_DESCR.REG_ANY)}""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX, ASM_DESCR.CLOBBER_RDX, ASM_DESCR.CLOBBER_R8])
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@__attribute__(packed)
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def _cpuid_naked():
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__asm__(f"""push rbx
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mov eax, ecx
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cpuid
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mov dword ptr [rdx], eax
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mov dword ptr [rdx + 4], ebx
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mov dword ptr [rdx + 8], ecx
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mov dword ptr [rdx + 12], edx
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pop rbx
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ret""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX,
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ASM_DESCR.CLOBBER_RDX])
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@__attribute__(packed)
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def _cpuid_sub_naked():
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__asm__(f"""push rbx
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mov eax, ecx
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mov ecx, r8d
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cpuid
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mov dword ptr [rdx], eax
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mov dword ptr [rdx + 4], ebx
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mov dword ptr [rdx + 8], ecx
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mov dword ptr [rdx + 12], edx
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pop rbx
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ret""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX,
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ASM_DESCR.CLOBBER_RDX])
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@__attribute__(noinline)
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def cpuid(leaf: uint32, out: cpuid_result*):
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func: callable = _cpuid_naked
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__asm__(f"""mov ecx, {asminp(leaf, ASM_DESCR.REG_ANY)}
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mov rdx, {asminp(out, ASM_DESCR.REG_ANY)}
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call {asminp(func, ASM_DESCR.REG_ANY)}""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX,
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ASM_DESCR.CLOBBER_RDX, ASM_DESCR.CLOBBER_R8,
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ASM_DESCR.CLOBBER_R9, ASM_DESCR.CLOBBER_R10,
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ASM_DESCR.CLOBBER_R11])
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@__attribute__(noinline)
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def cpuid_sub(leaf: uint32, sub: uint32, out: cpuid_result*):
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func: callable = _cpuid_sub_naked
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__asm__(f"""mov ecx, {asminp(leaf, ASM_DESCR.REG_ANY)}
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mov r8d, {asminp(sub, ASM_DESCR.REG_ANY)}
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mov rdx, {asminp(out, ASM_DESCR.REG_ANY)}
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call {asminp(func, ASM_DESCR.REG_ANY)}""",
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op=[ASM_DESCR.CLOBBER_RAX, ASM_DESCR.CLOBBER_RCX,
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ASM_DESCR.CLOBBER_RDX, ASM_DESCR.CLOBBER_R8,
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ASM_DESCR.CLOBBER_R9, ASM_DESCR.CLOBBER_R10,
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ASM_DESCR.CLOBBER_R11])
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@__attribute__(noinline)
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def detect_features_static() -> uint32:
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features: uint32 = 0
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res: cpuid_result
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cpuid(1, &res)
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if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
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if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
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if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
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if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
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if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
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if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
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if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
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if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
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if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
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if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
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if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
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if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
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if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
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if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
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if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
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if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
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if res.edx & (1 << 21): features |= CPU_FEATURE_DS
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if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
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if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
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if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
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if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
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if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
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if res.edx & (1 << 27): features |= CPU_FEATURE_SS
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if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
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if res.edx & (1 << 29): features |= CPU_FEATURE_TM
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if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
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return features
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@__attribute__(packed)
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class per_cpu_data:
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user_rsp: uint64
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kernel_rsp0: uint64
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current_pid: int
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_pad0: uint32
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_pad1: uint64
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_per_cpu: per_cpu_data
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class _CPUObject:
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tss: _tss
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features: uint32
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def __init__(self):
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self.__init_tss__()
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def __init_tss__(self):
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global _per_cpu
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string.memset(&self.tss, 0, self.tss.__sizeof__())
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self.tss.io_map_base = self.tss.__sizeof__()
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string.memset(&_per_cpu, 0, per_cpu_data.__sizeof__())
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gdt.setTSS64(5, uint64(&self.tss), self.tss.__sizeof__() - 1)
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gdt.flush()
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# IA32_KERNEL_GS_BASE holds the per_cpu address for swapgs.
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# When entering from Ring 3, swapgs swaps IA32_GS_BASE (0) with
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# IA32_KERNEL_GS_BASE (_per_cpu), making gs: accessible in kernel.
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# When returning to Ring 3, swapgs swaps back, restoring GS base to 0.
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msr_write(IA32_KERNEL_GS_BASE, uint64(&_per_cpu))
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def getInfo(self, info: cpu_info*):
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if not info: return
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res: cpuid_result
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cpuid(0, &res)
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uint32*(info.vendor_id)[0] = res.ebx
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uint32*(info.vendor_id)[1] = res.edx
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uint32*(info.vendor_id)[2] = res.ecx
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info.vendor_id[12] = '\0'
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info.features = self.detectFeatures()
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cpuid(1, &res)
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info.stepping = (res.eax >> 0) & 0x0F
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info.model = (res.eax >> 4) & 0x0F
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info.family = (res.eax >> 8) & 0x0F
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info.cpu_type = (res.eax >> 12) & 0x03
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info.ext_model = (res.eax >> 16) & 0x0F
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info.ext_family = (res.eax >> 20) & 0xFF
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# CPUID 品牌串：0x80000002..0x80000004 共 3 个叶 × 16 字节 = 48，
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# 与 brand_string[48] 等长（此前 range(4) 会写 64 字节 → 越界 16 字节）。
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# 逐 u32 按字节地址显式写入，避免 uint32|t.CPtr 被降级为 i8* 后
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# 下标按字节偏移且被截断为 i8（只写低字节、偏移不乘 4）。
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brand_addr: uint64 = uint64(uint32*(info.brand_string))
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for i in range(3):
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cpuid(0x80000002 + i, &res)
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off_b: uint64 = uint64(i) * 16
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*(uint32*(brand_addr + off_b + 0)) = res.eax
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*(uint32*(brand_addr + off_b + 4)) = res.ebx
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*(uint32*(brand_addr + off_b + 8)) = res.ecx
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*(uint32*(brand_addr + off_b + 12)) = res.edx
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info.brand_string[47] = '\0'
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info.cpu_freq = 2000000000
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def detectFeatures(self) -> uint32:
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features: int32 = 0
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res: cpuid_result
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cpuid(1, &res)
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if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
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if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
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if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
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if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
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if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
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if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
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if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
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if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
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if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
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if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
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if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
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if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
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if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
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if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
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if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
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if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
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if res.edx & (1 << 21): features |= CPU_FEATURE_DS
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if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
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if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
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if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
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if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
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if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
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if res.edx & (1 << 27): features |= CPU_FEATURE_SS
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if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
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if res.edx & (1 << 29): features |= CPU_FEATURE_TM
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if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
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return features
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def enableInterrupts(self):
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__asm__("sti", [ASM_DESCR.CLOBBER_MEMORY])
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def disableInterrupts(self):
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__asm__("cli", [ASM_DESCR.CLOBBER_MEMORY])
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def enableNmis(self):
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current: uint8 = asm.inb(0x70)
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asm.outb(0x70, current & 0x7F)
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def disableNmis(self):
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current: uint8 = asm.inb(0x70)
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asm.outb(0x70, current | 0x80)
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def readCR0(self) -> uint64:
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cr0: uint64
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__asm__(f"""mov rax, cr0
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mov {asmout(cr0, ASM_DESCR.OUTPUT_REG)}, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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return cr0
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def writeCR0(self, value: uint64):
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__asm__(f"""mov rax, {asminp(value, ASM_DESCR.REG_ANY)}
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mov cr0, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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def readCR3(self) -> uint64:
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cr3: uint64
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__asm__(f"""mov rax, cr3
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mov {asmout(cr3, ASM_DESCR.OUTPUT_REG)}, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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return cr3
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def writeCR3(self, value: uint64):
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__asm__(f"""mov rax, {asminp(value, ASM_DESCR.REG_ANY)}
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mov cr3, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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def readCR4(self) -> uint64:
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cr4: uint64
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__asm__(f"""mov rax, cr4
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mov {asmout(cr4, ASM_DESCR.OUTPUT_REG)}, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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return cr4
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def writeCR4(self, value: uint64):
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__asm__(f"""mov rax, {asminp(value, ASM_DESCR.REG_ANY)}
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mov cr4, rax""",
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[ASM_DESCR.CLOBBER_RAX])
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def readMSR(self, msr: uint32) -> uint64:
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return msr_read(msr)
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def writeMSR(self, msr: uint32, value: uint64):
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msr_write(msr, value)
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def setTSSRSP0(self, rsp0: uint64):
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global _per_cpu
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self.tss.rsp0 = rsp0
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_per_cpu.kernel_rsp0 = rsp0
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def set_kernel_rsp0(rsp0: uint64):
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global _per_cpu
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_per_cpu.kernel_rsp0 = rsp0
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# 启用 SSE/FPU：CR4.OSFXSR(bit9)|OSXMMEXCPT(bit10) 置位、CR0 清 EM(bit2) 置 MP(bit1)。
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# OVMF/UEFI 启动后 CR4.OSFXSR 未置位，任何 movaps 都 #GP(err=0)——变参函数
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# 传 float/double 时保存 xmm 寄存器触发（serial.printf / snprintf("%.2f") 崩溃根因）。
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def enable_sse():
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cr0_v: uint64 = 0
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__asm__(f"""mov rax, cr0
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mov {asmout(cr0_v, ASM_DESCR.OUTPUT_REG)}, rax""",
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op=[ASM_DESCR.CLOBBER_RAX])
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cr0_v = cr0_v & ~uint64(4) # 清 EM（禁止 FPU 仿真）
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cr0_v = cr0_v | uint64(2) # 置 MP（监控协处理器）
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__asm__(f"""mov rax, {asminp(cr0_v, ASM_DESCR.REG_ANY)}
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mov cr0, rax""",
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op=[ASM_DESCR.CLOBBER_RAX])
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cr4_v: uint64 = 0
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__asm__(f"""mov rax, cr4
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mov {asmout(cr4_v, ASM_DESCR.OUTPUT_REG)}, rax""",
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op=[ASM_DESCR.CLOBBER_RAX])
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cr4_v = cr4_v | uint64(0x600) # OSFXSR | OSXMMEXCPT
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__asm__(f"""mov rax, {asminp(cr4_v, ASM_DESCR.REG_ANY)}
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mov cr4, rax""",
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op=[ASM_DESCR.CLOBBER_RAX])
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__asm__("fninit", op=[ASM_DESCR.CLOBBER_MEMORY])
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