303 lines
13 KiB
Plaintext
303 lines
13 KiB
Plaintext
import drivers.serial.uart.serial as serial
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import viperlib
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import t, c
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PTE_PRESENT: t.CDefine = (1 << 0)
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PTE_WRITABLE: t.CDefine = (1 << 1)
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PTE_USER: t.CDefine = (1 << 2)
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PTE_PWT: t.CDefine = (1 << 3)
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PTE_PCD: t.CDefine = (1 << 4)
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PTE_ACCESSED: t.CDefine = (1 << 5)
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PTE_DIRTY: t.CDefine = (1 << 6)
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PTE_PS: t.CDefine = (1 << 7)
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PTE_GLOBAL: t.CDefine = (1 << 8)
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class _p:
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entries: t.CArray[t.CUInt64T, 512]
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PT_POOL_PAGES: t.CDefine = 512
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pt_pool_raw: t.CVoid | t.CPtr = None
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pt_pool_start: t.CUInt64T = 0
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pt_pool_used: t.CUInt64T = 0
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AllocatedPages: t.CUInt64T = 0
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pml4: _p | t.CPtr = None
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pdp: _p | t.CPtr
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pd: _p | t.CPtr
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pt: _p | t.CPtr
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def init(MemmapAddr: t.CUInt64T, MemmapSize: t.CUInt64T):
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global pml4
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pml4 = GetCurrentPml4()
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c.Asm(f"""
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mov rax, cr0
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and rax, ~0x10000
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mov cr0, rax
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""")
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def init_pool(buf: t.CVoid | t.CPtr, buf_size: t.CUInt64T):
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global pt_pool_raw, pt_pool_start, pt_pool_used
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pt_pool_raw = buf
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if buf is None: return
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raw_addr: t.CUInt64T = t.CUInt64T(buf)
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aligned_addr: t.CUInt64T = (raw_addr + t.CUInt64T(0xFFF)) & ~t.CUInt64T(0xFFF)
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pt_pool_start = aligned_addr
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pt_pool_used = 0
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def AllocPage() -> t.CVoid | t.CPtr:
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global AllocatedPages, pt_pool_used, pml4, pdp, pd, pt
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if pt_pool_raw is None: return None
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if pt_pool_used >= t.CUInt64T(PT_POOL_PAGES): return None
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page: t.CVoid | t.CPtr = t.CVoid(pt_pool_start + pt_pool_used * t.CUInt64T(4096), t.CPtr)
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pt_pool_used = pt_pool_used + t.CUInt64T(1)
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c.Asm(f"""mov al, 0
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mov ecx, 4096
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mov rdi, {c.AsmInp(page, t.ASM_DESCR.REG_ANY)}
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rep stosb""",
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op = [t.ASM_DESCR.CLOBBER_AL, t.ASM_DESCR.CLOBBER_ECX, t.ASM_DESCR.CLOBBER_RDI])
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AllocatedPages = AllocatedPages + t.CUInt64T(1)
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return page
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def FreePage(page: t.CVoid | t.CPtr):
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global AllocatedPages, pml4, pdp, pd, pt
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if page is None: return
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if AllocatedPages > 0: AllocatedPages = AllocatedPages - t.CUInt64T(1)
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def MapPage(VirtAddr: t.CUInt64T, PhysAddr: t.CUInt64T, flags: t.CUInt64T):
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global pml4, pdp, pd, pt
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if VirtAddr == 0 or PhysAddr == 0: return
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VirtAddr = VirtAddr & ~t.CUInt64T(0xFFF)
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PhysAddr = PhysAddr & ~t.CUInt64T(0xFFF)
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Pml4Index: t.CUInt64T = (VirtAddr >> 39) & 0x1FF
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PdpIndex: t.CUInt64T = (VirtAddr >> 30) & 0x1FF
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PdIndex: t.CUInt64T = (VirtAddr >> 21) & 0x1FF
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PtIndex: t.CUInt64T = (VirtAddr >> 12) & 0x1FF
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if not pml4:
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pml4 = AllocPage()
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if not pml4: return
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if not (pml4.entries[Pml4Index] & PTE_PRESENT):
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pdp: _p | t.CPtr = AllocPage()
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if not pdp: return
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pml4.entries[Pml4Index] = (t.CUInt64T(pdp) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE | (flags & PTE_USER)
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else:
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if (flags & PTE_USER) and not (pml4.entries[Pml4Index] & PTE_USER):
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pml4.entries[Pml4Index] = pml4.entries[Pml4Index] | PTE_USER
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pdp: _p | t.CPtr = t.CType(pml4.entries[Pml4Index] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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if not (pdp.entries[PdpIndex] & PTE_PRESENT):
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pd: _p | t.CPtr = AllocPage()
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if not pd: return
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pdp.entries[PdpIndex] = (t.CUInt64T(pd) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE | (flags & PTE_USER)
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else:
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if (flags & PTE_USER) and not (pdp.entries[PdpIndex] & PTE_USER):
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pdp.entries[PdpIndex] = pdp.entries[PdpIndex] | PTE_USER
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pd: _p | t.CPtr = t.CType(pdp.entries[PdpIndex] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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if pd.entries[PdIndex] & 1:
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if pd.entries[PdIndex] & 0x80:
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big_phys: t.CUInt64T = pd.entries[PdIndex] & ~t.CUInt64T(0x1FFFFF)
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inherit_flags: t.CUInt64T = pd.entries[PdIndex] & (PTE_PCD | PTE_PWT)
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pt: _p | t.CPtr = AllocPage()
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if not pt: return
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split_i: t.CInt = 0
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while split_i < 512:
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pt.entries[split_i] = (big_phys + t.CUInt64T(split_i) * 0x1000) | PTE_PRESENT | PTE_WRITABLE | inherit_flags
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split_i += 1
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pd.entries[PdIndex] = (t.CUInt64T(pt) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE | (flags & PTE_USER)
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else:
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# PD entry exists as a regular PT (e.g. cloned identity mapping).
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# Must propagate PTE_USER to the PD entry so user-mode access is
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# allowed at all paging levels, otherwise #PF err=0x5.
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if (flags & PTE_USER) and not (pd.entries[PdIndex] & PTE_USER):
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pd.entries[PdIndex] = pd.entries[PdIndex] | PTE_USER
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else:
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pt: _p | t.CPtr = AllocPage()
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if not pt: return
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pd.entries[PdIndex] = (t.CUInt64T(pt) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE | (flags & PTE_USER)
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pt: _p | t.CPtr = t.CType(pd.entries[PdIndex] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pt.entries[PtIndex] = PhysAddr | flags | PTE_PRESENT
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c.Asm(f"invlpg [{c.AsmInp(VirtAddr, t.ASM_DESCR.REG_ANY)}]")
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def MapLargePage(VirtAddr: t.CUInt64T, PhysAddr: t.CUInt64T, flags: t.CUInt64T) -> t.CVoid:
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global pml4, pdp, pd, pt
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VirtAddr = VirtAddr & ~t.CUInt64T(0x1FFFFF)
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PhysAddr = PhysAddr & ~t.CUInt64T(0x1FFFFF)
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Pml4Index: t.CUInt64T = (VirtAddr >> 39) & 0x1FF
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PdpIndex: t.CUInt64T = (VirtAddr >> 30) & 0x1FF
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PdIndex: t.CUInt64T = (VirtAddr >> 21) & 0x1FF
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if not pml4:
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pml4 = AllocPage()
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if not pml4: return
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if not pml4.entries[Pml4Index] & PTE_PRESENT:
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pdp: _p | t.CPtr = AllocPage()
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if not pdp: return
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pml4.entries[Pml4Index] = (t.CUInt64T(pdp) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE
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pdp: _p | t.CPtr = t.CType(pml4.entries[Pml4Index] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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if not (pdp.entries[PdpIndex] & PTE_PRESENT):
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pd: _p | t.CPtr = AllocPage()
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if not pd: return
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pdp.entries[PdpIndex] = (t.CUInt64T(pd) & ~t.CUInt64T(0xFFF)) | PTE_PRESENT | PTE_WRITABLE
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pd: _p | t.CPtr = t.CType(pdp.entries[PdpIndex] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pd.entries[PdIndex] = PhysAddr | flags | PTE_PRESENT | PTE_PS
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c.Asm(f"invlpg [{c.AsmInp(VirtAddr, t.ASM_DESCR.REG_ANY)}]")
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def UnMapPage(VirtAddr: t.CUInt64T):
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global pml4, pdp, pd, pt
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if VirtAddr == 0: return
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if not pml4: return
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Pml4Index: t.CUInt64T = (VirtAddr >> 39) & 0x1FF
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PdpIndex: t.CUInt64T = (VirtAddr >> 30) & 0x1FF
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PdIndex: t.CUInt64T = (VirtAddr >> 21) & 0x1FF
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PtIndex: t.CUInt64T = (VirtAddr >> 12) & 0x1FF
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if not pml4.entries[Pml4Index] & PTE_PRESENT: return
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pdp: _p | t.CPtr = t.CType(pml4.entries[Pml4Index] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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if not pdp.entries[PdpIndex] & PTE_PRESENT: return
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pd: _p | t.CPtr = t.CType(pdp.entries[PdpIndex] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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if not pd.entries[PdIndex] & PTE_PRESENT: return
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if pd.entries[PdIndex] & PTE_PS:
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pd.entries[PdIndex] = 0
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else:
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pt: _p | t.CPtr = t.CType(pd.entries[PdIndex] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pt.entries[PtIndex] = 0
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c.Asm(f"invlpg [{c.AsmInp(VirtAddr, t.ASM_DESCR.REG_ANY)}]")
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def EnablePaging():
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global pml4, pdp, pd, pt
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c.Asm(f"mov cr3, {c.AsmInp(t.CUInt64T(pml4), t.ASM_DESCR.REG_ANY)}")
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def GetCurrentPml4() -> _p | t.CPtr:
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global pml4, pdp, pd, pt
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cr3: t.CUInt64T
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c.Asm(f"mov {c.AsmOut(cr3, t.ASM_DESCR.OUTPUT_REG)}, cr3")
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return (_p | t.CPtr)(cr3 & ~t.CUInt64T(0xFFF))
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def create_process_page_table() -> t.CUInt64T:
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global pml4
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if not pml4: return 0
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new_pml4: _p | t.CPtr = AllocPage()
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if not new_pml4: return 0
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i: t.CUInt64T
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for i in range(512):
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entry: t.CUInt64T = pml4.entries[i]
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if entry & PTE_PRESENT:
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new_pml4.entries[i] = entry
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return t.CUInt64T(new_pml4)
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def clone_for_process(isolate_vaddr: t.CUInt64T) -> t.CUInt64T:
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global pml4
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_dbg: t.CArray[t.CChar, 120]
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viperlib.snprintf(c.Addr(_dbg), 120, "[clone] pml4=0x%lx pool_used=%lu iso_va=0x%lx\n", t.CUInt64T(pml4), pt_pool_used, isolate_vaddr)
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serial.puts(_dbg)
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if not pml4: return 0
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new_pml4_page: _p | t.CPtr = AllocPage()
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if not new_pml4_page:
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# [DIAG] 定位 AllocPage 失败：pool_used 打印 0 但分配失败 → BSS 全局
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# （pt_pool_raw/pt_pool_used）疑似被内存越界写覆盖。
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_dbgf: t.CArray[t.CChar, 120]
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viperlib.snprintf(c.Addr(_dbgf), 120, "[clone] AllocPage FAIL raw=0x%lx used=%lu PP=%d\n",
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t.CUInt64T(pt_pool_raw), pt_pool_used, PT_POOL_PAGES)
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serial.puts(c.Addr(_dbgf))
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serial.puts("[clone] AllocPage pml4 failed\n")
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return 0
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_dbg2: t.CArray[t.CChar, 120]
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viperlib.snprintf(c.Addr(_dbg2), 120, "[clone] new_pml4=0x%lx\n", t.CUInt64T(new_pml4_page))
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serial.puts(_dbg2)
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i: t.CUInt64T
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for i in range(512):
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new_pml4_page.entries[i] = pml4.entries[i]
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pml4_idx: t.CUInt64T = (isolate_vaddr >> 39) & 0x1FF
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_dbg3: t.CArray[t.CChar, 120]
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viperlib.snprintf(c.Addr(_dbg3), 120, "[clone] pml4_idx=%lu entry0=0x%lx\n", pml4_idx, pml4.entries[pml4_idx])
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serial.puts(_dbg3)
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if not (pml4.entries[pml4_idx] & PTE_PRESENT): return t.CUInt64T(new_pml4_page)
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kernel_pdp: _p | t.CPtr = t.CType(pml4.entries[pml4_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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new_pdp_page: _p | t.CPtr = AllocPage()
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if not new_pdp_page: return t.CUInt64T(new_pml4_page)
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for i in range(512):
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new_pdp_page.entries[i] = kernel_pdp.entries[i]
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new_pml4_page.entries[pml4_idx] = (t.CUInt64T(new_pdp_page) & ~t.CUInt64T(0xFFF)) | (pml4.entries[pml4_idx] & t.CUInt64T(0xFFF))
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pdp_idx: t.CUInt64T = (isolate_vaddr >> 30) & 0x1FF
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if not (kernel_pdp.entries[pdp_idx] & PTE_PRESENT): return t.CUInt64T(new_pml4_page)
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kernel_pd: _p | t.CPtr = t.CType(kernel_pdp.entries[pdp_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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new_pd_page: _p | t.CPtr = AllocPage()
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if not new_pd_page: return t.CUInt64T(new_pml4_page)
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for i in range(512):
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new_pd_page.entries[i] = kernel_pd.entries[i]
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new_pdp_page.entries[pdp_idx] = (t.CUInt64T(new_pd_page) & ~t.CUInt64T(0xFFF)) | (kernel_pdp.entries[pdp_idx] & t.CUInt64T(0xFFF))
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pd_idx: t.CUInt64T = (isolate_vaddr >> 21) & 0x1FF
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if not (kernel_pd.entries[pd_idx] & PTE_PRESENT): return t.CUInt64T(new_pml4_page)
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if kernel_pd.entries[pd_idx] & PTE_PS: return t.CUInt64T(new_pml4_page)
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kernel_pt: _p | t.CPtr = t.CType(kernel_pd.entries[pd_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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new_pt_page: _p | t.CPtr = AllocPage()
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if not new_pt_page: return t.CUInt64T(new_pml4_page)
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for i in range(512):
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new_pt_page.entries[i] = kernel_pt.entries[i]
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new_pd_page.entries[pd_idx] = (t.CUInt64T(new_pt_page) & ~t.CUInt64T(0xFFF)) | (kernel_pd.entries[pd_idx] & t.CUInt64T(0xFFF))
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return t.CUInt64T(new_pml4_page)
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def save_pt_range(vaddr_start: t.CUInt64T, vaddr_end: t.CUInt64T, save_buf: t.CUInt64T | t.CPtr, save_count: t.CUInt32T | t.CPtr) -> t.CInt:
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global pml4
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if not pml4: return -1
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c.Set(save_count, t.CUInt32T(0))
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va: t.CUInt64T = vaddr_start & ~t.CUInt64T(0xFFF)
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while va < vaddr_end:
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pml4_idx: t.CUInt64T = (va >> 39) & 0x1FF
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if not (pml4.entries[pml4_idx] & PTE_PRESENT): va += 0x1000; continue
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pdp_: _p | t.CPtr = t.CType(pml4.entries[pml4_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pdp_idx: t.CUInt64T = (va >> 30) & 0x1FF
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if not (pdp_.entries[pdp_idx] & PTE_PRESENT): va += 0x1000; continue
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pd_: _p | t.CPtr = t.CType(pdp_.entries[pdp_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pd_idx: t.CUInt64T = (va >> 21) & 0x1FF
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if not (pd_.entries[pd_idx] & PTE_PRESENT): va += 0x1000; continue
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if pd_.entries[pd_idx] & PTE_PS: va += 0x200000; continue
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pt_: _p | t.CPtr = t.CType(pd_.entries[pd_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pt_idx: t.CUInt64T = (va >> 12) & 0x1FF
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saved: t.CUInt32T = c.DerefAs(save_count)
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entry_ptr: t.CUInt64T | t.CPtr = save_buf + t.CUInt64T(saved) * 16
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c.DerefAs(entry_ptr, va)
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c.DerefAs(entry_ptr + 8, pt_.entries[pt_idx])
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c.Set(save_count, t.CUInt32T(saved + 1))
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va += 0x1000
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return 0
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def restore_pt_range(save_buf: t.CUInt64T | t.CPtr, save_count: t.CUInt32T):
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global pml4
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if not pml4: return
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i: t.CUInt32T = 0
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while i < save_count:
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entry_ptr: t.CUInt64T | t.CPtr = save_buf + t.CUInt64T(i) * 16
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va: t.CUInt64T = c.DerefAs(entry_ptr)
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orig_pte: t.CUInt64T = c.DerefAs(entry_ptr + 8)
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pml4_idx: t.CUInt64T = (va >> 39) & 0x1FF
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if not (pml4.entries[pml4_idx] & PTE_PRESENT): i += 1; continue
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pdp_: _p | t.CPtr = t.CType(pml4.entries[pml4_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pdp_idx: t.CUInt64T = (va >> 30) & 0x1FF
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if not (pdp_.entries[pdp_idx] & PTE_PRESENT): i += 1; continue
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pd_: _p | t.CPtr = t.CType(pdp_.entries[pdp_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pd_idx: t.CUInt64T = (va >> 21) & 0x1FF
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if not (pd_.entries[pd_idx] & PTE_PRESENT): i += 1; continue
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if pd_.entries[pd_idx] & PTE_PS: i += 1; continue
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pt_: _p | t.CPtr = t.CType(pd_.entries[pd_idx] & ~t.CUInt64T(0xFFF), _p, t.CPtr)
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pt_idx: t.CUInt64T = (va >> 12) & 0x1FF
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pt_.entries[pt_idx] = orig_pte
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c.Asm(f"invlpg [{c.AsmInp(va, t.ASM_DESCR.REG_ANY)}]", op=[t.ASM_DESCR.CLOBBER_MEMORY])
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i += 1
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def set_active_pml4(cr3_val: t.CUInt64T):
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global pml4
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pml4 = (_p | t.CPtr)(cr3_val & ~t.CUInt64T(0xFFF))
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