TermiNexus
7b084803f5
faulting RSP=0x7d760 16 对齐证明非栈对齐问题，movaps #GP(err=0) 真因是 CR4.OSFXSR 未置位（SSE 未启用）。OVMF 启动后 SSE 默认关闭，变参函数传 float/double 保存 xmm 寄存器时触发。新增 cpu.enable_sse（CR0 清 EM 置 MP + CR4 OSFXSR|OSXMMEXCPT + fninit），main.vp __init__ 开头调用。
370 lines
14 KiB
Plaintext
370 lines
14 KiB
Plaintext
import fpu
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import asm
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import intr.gdt as gdt
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import string
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import t, c
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IA32_KERNEL_GS_BASE: t.CDefine = 0xC0000102
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KERN_STACK_SIZE: t.CDefine = 8192
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CPU_FEATURE_FPU: t.CDefine = (1 << 0)
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CPU_FEATURE_PSE: t.CDefine = (1 << 1)
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CPU_FEATURE_MSR: t.CDefine = (1 << 2)
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CPU_FEATURE_PAE: t.CDefine = (1 << 3)
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CPU_FEATURE_MCE: t.CDefine = (1 << 4)
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CPU_FEATURE_CX8: t.CDefine = (1 << 5)
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CPU_FEATURE_APIC: t.CDefine = (1 << 6)
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CPU_FEATURE_SEP: t.CDefine = (1 << 7)
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CPU_FEATURE_MTRR: t.CDefine = (1 << 8)
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CPU_FEATURE_PGE: t.CDefine = (1 << 9)
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CPU_FEATURE_MCA: t.CDefine = (1 << 10)
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CPU_FEATURE_CMOV: t.CDefine = (1 << 11)
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CPU_FEATURE_PAT: t.CDefine = (1 << 12)
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CPU_FEATURE_PSE36: t.CDefine = (1 << 13)
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CPU_FEATURE_PSN: t.CDefine = (1 << 14)
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CPU_FEATURE_CLFSH: t.CDefine = (1 << 15)
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CPU_FEATURE_DS: t.CDefine = (1 << 16)
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CPU_FEATURE_ACPI: t.CDefine = (1 << 17)
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CPU_FEATURE_MMX: t.CDefine = (1 << 18)
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CPU_FEATURE_FXSR: t.CDefine = (1 << 19)
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CPU_FEATURE_SSE: t.CDefine = (1 << 20)
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CPU_FEATURE_SSE2: t.CDefine = (1 << 21)
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CPU_FEATURE_SS: t.CDefine = (1 << 22)
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CPU_FEATURE_HTT: t.CDefine = (1 << 23)
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CPU_FEATURE_TM: t.CDefine = (1 << 24)
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CPU_FEATURE_PBE: t.CDefine = (1 << 25)
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class cpu_info(t.CStruct):
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vendor_id: t.CArray[t.CChar, 13]
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brand_string: t.CArray[t.CChar, 48]
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features: t.CUInt32T
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family: t.CUInt32T
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model: t.CUInt32T
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stepping: t.CUInt32T
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cpu_type: t.CUInt32T
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ext_model: t.CUInt32T
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ext_family: t.CUInt32T
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cpu_freq: t.CUInt64T
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@c.Attribute(t.attr.packed)
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class _tss:
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reserved0: t.CUInt64T
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rsp0: t.CUInt64T
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rsp1: t.CUInt64T
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rsp2: t.CUInt64T
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reserved1: t.CUInt64T
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ist1: t.CUInt64T
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ist2: t.CUInt64T
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ist3: t.CUInt64T
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ist4: t.CUInt64T
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ist5: t.CUInt64T
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ist6: t.CUInt64T
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ist7: t.CUInt64T
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reserved2: t.CUInt64T
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reserved3: t.CUInt16T
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io_map_base: t.CUInt16T
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class cpuid_result(t.CStruct):
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eax: t.CUInt32T
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ebx: t.CUInt32T
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ecx: t.CUInt32T
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edx: t.CUInt32T
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@c.Attribute(t.attr.naked)
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def _rdmsr_naked():
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c.Asm(f"""rdmsr
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shl rdx, 32
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or rax, rdx
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RDX])
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@c.Attribute(t.attr.naked)
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def _wrmsr_naked():
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# msr_write sets ecx=msr, r8=value. wrmsr needs ECX=msr, EDX:EAX=value.
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# Old code did `mov rax,rcx` (rax=msr) which wrote (value>>32):msr to MSR,
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# corrupting IA32_KERNEL_GS_BASE -> swapgs -> #GP on gs:[0]. Fixed below.
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c.Asm(f"""mov rax, r8
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mov rdx, r8
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shr rdx, 32
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wrmsr
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RDX])
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def msr_read(msr: t.CUInt32T) -> t.CUInt64T:
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result: t.CUInt64T = 0
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func: t.CVoid | t.CPtr = _rdmsr_naked
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c.Asm(f"""mov ecx, {c.AsmInp(msr, t.ASM_DESCR.REG_ANY)}
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call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}
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mov {c.AsmOut(result, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX, t.ASM_DESCR.CLOBBER_RDX])
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return result
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def msr_write(msr: t.CUInt32T, value: t.CUInt64T):
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func: t.CVoid | t.CPtr = _wrmsr_naked
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c.Asm(f"""mov ecx, {c.AsmInp(msr, t.ASM_DESCR.REG_ANY)}
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mov r8, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
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call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX, t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8])
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@c.Attribute(t.attr.naked)
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def _cpuid_naked():
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c.Asm(f"""push rbx
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mov eax, ecx
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cpuid
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mov dword ptr [rdx], eax
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mov dword ptr [rdx + 4], ebx
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mov dword ptr [rdx + 8], ecx
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mov dword ptr [rdx + 12], edx
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pop rbx
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
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t.ASM_DESCR.CLOBBER_RDX])
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@c.Attribute(t.attr.naked)
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def _cpuid_sub_naked():
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c.Asm(f"""push rbx
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mov eax, ecx
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mov ecx, r8d
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cpuid
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mov dword ptr [rdx], eax
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mov dword ptr [rdx + 4], ebx
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mov dword ptr [rdx + 8], ecx
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mov dword ptr [rdx + 12], edx
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pop rbx
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ret""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
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t.ASM_DESCR.CLOBBER_RDX])
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@c.Attribute(t.attr.noinline)
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def cpuid(leaf: t.CUInt32T, out: cpuid_result | t.CPtr):
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func: t.CVoid | t.CPtr = _cpuid_naked
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c.Asm(f"""mov ecx, {c.AsmInp(leaf, t.ASM_DESCR.REG_ANY)}
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mov rdx, {c.AsmInp(out, t.ASM_DESCR.REG_ANY)}
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call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
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t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8,
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t.ASM_DESCR.CLOBBER_R9, t.ASM_DESCR.CLOBBER_R10,
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t.ASM_DESCR.CLOBBER_R11])
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@c.Attribute(t.attr.noinline)
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def cpuid_sub(leaf: t.CUInt32T, sub: t.CUInt32T, out: cpuid_result | t.CPtr):
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func: t.CVoid | t.CPtr = _cpuid_sub_naked
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c.Asm(f"""mov ecx, {c.AsmInp(leaf, t.ASM_DESCR.REG_ANY)}
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mov r8d, {c.AsmInp(sub, t.ASM_DESCR.REG_ANY)}
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mov rdx, {c.AsmInp(out, t.ASM_DESCR.REG_ANY)}
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call {c.AsmInp(func, t.ASM_DESCR.REG_ANY)}""",
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op=[t.ASM_DESCR.CLOBBER_RAX, t.ASM_DESCR.CLOBBER_RCX,
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t.ASM_DESCR.CLOBBER_RDX, t.ASM_DESCR.CLOBBER_R8,
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t.ASM_DESCR.CLOBBER_R9, t.ASM_DESCR.CLOBBER_R10,
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t.ASM_DESCR.CLOBBER_R11])
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@c.Attribute(t.attr.noinline)
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def detect_features_static() -> t.CUInt32T:
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features: t.CUInt32T = 0
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res: cpuid_result
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cpuid(1, c.Addr(res))
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if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
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if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
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if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
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if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
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if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
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if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
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if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
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if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
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if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
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if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
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if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
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if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
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if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
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if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
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if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
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if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
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if res.edx & (1 << 21): features |= CPU_FEATURE_DS
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if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
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if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
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if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
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if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
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if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
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if res.edx & (1 << 27): features |= CPU_FEATURE_SS
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if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
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if res.edx & (1 << 29): features |= CPU_FEATURE_TM
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if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
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return features
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@c.Attribute(t.attr.packed)
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class per_cpu_data:
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user_rsp: t.CUInt64T
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kernel_rsp0: t.CUInt64T
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current_pid: t.CInt
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_pad0: t.CUInt32T
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_pad1: t.CUInt64T
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_per_cpu: per_cpu_data
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@t.Object
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class _CPUObject:
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tss: _tss
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features: t.CUInt32T
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def __init__(self):
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self.__init_tss__()
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def __init_tss__(self):
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global _per_cpu
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string.memset(c.Addr(self.tss), 0, self.tss.__sizeof__())
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self.tss.io_map_base = self.tss.__sizeof__()
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string.memset(c.Addr(_per_cpu), 0, per_cpu_data.__sizeof__())
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gdt.setTSS64(5, t.CUInt64T(c.Addr(self.tss)), self.tss.__sizeof__() - 1)
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gdt.flush()
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# IA32_KERNEL_GS_BASE holds the per_cpu address for swapgs.
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# When entering from Ring 3, swapgs swaps IA32_GS_BASE (0) with
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# IA32_KERNEL_GS_BASE (_per_cpu), making gs: accessible in kernel.
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# When returning to Ring 3, swapgs swaps back, restoring GS base to 0.
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msr_write(IA32_KERNEL_GS_BASE, t.CUInt64T(c.Addr(_per_cpu)))
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def getInfo(self, info: cpu_info | t.CPtr):
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if not info: return
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res: cpuid_result
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cpuid(0, c.Addr(res))
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(t.CUInt32T(info.vendor_id, t.CPtr))[0] = res.ebx
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(t.CUInt32T(info.vendor_id, t.CPtr))[1] = res.edx
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(t.CUInt32T(info.vendor_id, t.CPtr))[2] = res.ecx
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info.vendor_id[12] = '\0'
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info.features = self.detectFeatures()
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cpuid(1, c.Addr(res))
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info.stepping = (res.eax >> 0) & 0x0F
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info.model = (res.eax >> 4) & 0x0F
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info.family = (res.eax >> 8) & 0x0F
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info.cpu_type = (res.eax >> 12) & 0x03
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info.ext_model = (res.eax >> 16) & 0x0F
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info.ext_family = (res.eax >> 20) & 0xFF
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for i in range(4):
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cpuid(0x80000002 + i, c.Addr(res))
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base: t.CUInt32T | t.CPtr = t.CUInt32T(info.brand_string, t.CPtr)
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base[i * 4 + 0] = res.eax
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base[i * 4 + 1] = res.ebx
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base[i * 4 + 2] = res.ecx
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base[i * 4 + 3] = res.edx
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info.brand_string[47] = '\0'
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info.cpu_freq = 2000000000
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def detectFeatures(self) -> t.CUInt32T:
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features: t.CInt32T = 0
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res: cpuid_result
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cpuid(1, c.Addr(res))
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if res.edx & (1 << 0): features |= CPU_FEATURE_FPU
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if res.edx & (1 << 3): features |= CPU_FEATURE_PSE
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if res.edx & (1 << 5): features |= CPU_FEATURE_MSR
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if res.edx & (1 << 6): features |= CPU_FEATURE_PAE
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if res.edx & (1 << 7): features |= CPU_FEATURE_MCE
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if res.edx & (1 << 8): features |= CPU_FEATURE_CX8
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if res.edx & (1 << 9): features |= CPU_FEATURE_APIC
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if res.edx & (1 << 11): features |= CPU_FEATURE_SEP
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if res.edx & (1 << 12): features |= CPU_FEATURE_MTRR
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if res.edx & (1 << 13): features |= CPU_FEATURE_PGE
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if res.edx & (1 << 14): features |= CPU_FEATURE_MCA
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if res.edx & (1 << 15): features |= CPU_FEATURE_CMOV
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if res.edx & (1 << 16): features |= CPU_FEATURE_PAT
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if res.edx & (1 << 17): features |= CPU_FEATURE_PSE36
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if res.edx & (1 << 18): features |= CPU_FEATURE_PSN
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if res.edx & (1 << 19): features |= CPU_FEATURE_CLFSH
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if res.edx & (1 << 21): features |= CPU_FEATURE_DS
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if res.edx & (1 << 22): features |= CPU_FEATURE_ACPI
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if res.edx & (1 << 23): features |= CPU_FEATURE_MMX
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if res.edx & (1 << 24): features |= CPU_FEATURE_FXSR
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if res.edx & (1 << 25): features |= CPU_FEATURE_SSE
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if res.edx & (1 << 26): features |= CPU_FEATURE_SSE2
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if res.edx & (1 << 27): features |= CPU_FEATURE_SS
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if res.edx & (1 << 28): features |= CPU_FEATURE_HTT
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if res.edx & (1 << 29): features |= CPU_FEATURE_TM
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if res.edx & (1 << 30): features |= CPU_FEATURE_PBE
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return features
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def enableInterrupts(self):
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c.Asm("sti", [t.ASM_DESCR.CLOBBER_MEMORY])
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def disableInterrupts(self):
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c.Asm("cli", [t.ASM_DESCR.CLOBBER_MEMORY])
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def enableNmis(self):
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current: t.CUInt8T = asm.inb(0x70)
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asm.outb(0x70, current & 0x7F)
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def disableNmis(self):
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current: t.CUInt8T = asm.inb(0x70)
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asm.outb(0x70, current | 0x80)
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def readCR0(self) -> t.CUInt64T:
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cr0: t.CUInt64T
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c.Asm(f"""mov rax, cr0
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mov {c.AsmOut(cr0, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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return cr0
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def writeCR0(self, value: t.CUInt64T):
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c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
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mov cr0, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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def readCR3(self) -> t.CUInt64T:
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cr3: t.CUInt64T
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c.Asm(f"""mov rax, cr3
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mov {c.AsmOut(cr3, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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return cr3
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def writeCR3(self, value: t.CUInt64T):
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c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
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mov cr3, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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def readCR4(self) -> t.CUInt64T:
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cr4: t.CUInt64T
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c.Asm(f"""mov rax, cr4
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mov {c.AsmOut(cr4, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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return cr4
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def writeCR4(self, value: t.CUInt64T):
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c.Asm(f"""mov rax, {c.AsmInp(value, t.ASM_DESCR.REG_ANY)}
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mov cr4, rax""",
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[t.ASM_DESCR.CLOBBER_RAX])
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def readMSR(self, msr: t.CUInt32T) -> t.CUInt64T:
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return msr_read(msr)
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def writeMSR(self, msr: t.CUInt32T, value: t.CUInt64T):
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msr_write(msr, value)
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def setTSSRSP0(self, rsp0: t.CUInt64T):
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global _per_cpu
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self.tss.rsp0 = rsp0
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_per_cpu.kernel_rsp0 = rsp0
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def set_kernel_rsp0(rsp0: t.CUInt64T):
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global _per_cpu
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_per_cpu.kernel_rsp0 = rsp0
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# 启用 SSE/FPU：CR4.OSFXSR(bit9)|OSXMMEXCPT(bit10) 置位、CR0 清 EM(bit2) 置 MP(bit1)。
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# OVMF/UEFI 启动后 CR4.OSFXSR 未置位，任何 movaps 都 #GP(err=0)——变参函数
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# 传 float/double 时保存 xmm 寄存器触发（serial.printf / snprintf("%.2f") 崩溃根因）。
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def enable_sse():
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cr0_v: t.CUInt64T = 0
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c.Asm(f"""mov rax, cr0
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mov {c.AsmOut(cr0_v, t.ASM_DESCR.OUTPUT_REG)}, rax""",
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op=[t.ASM_DESCR.CLOBBER_RAX])
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cr0_v = cr0_v & ~t.CUInt64T(4) # 清 EM（禁止 FPU 仿真）
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cr0_v = cr0_v | t.CUInt64T(2) # 置 MP（监控协处理器）
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c.Asm(f"""mov rax, {c.AsmInp(cr0_v, t.ASM_DESCR.REG_ANY)}
|
||
mov cr0, rax""",
|
||
op=[t.ASM_DESCR.CLOBBER_RAX])
|
||
cr4_v: t.CUInt64T = 0
|
||
c.Asm(f"""mov rax, cr4
|
||
mov {c.AsmOut(cr4_v, t.ASM_DESCR.OUTPUT_REG)}, rax""",
|
||
op=[t.ASM_DESCR.CLOBBER_RAX])
|
||
cr4_v = cr4_v | t.CUInt64T(0x600) # OSFXSR | OSXMMEXCPT
|
||
c.Asm(f"""mov rax, {c.AsmInp(cr4_v, t.ASM_DESCR.REG_ANY)}
|
||
mov cr4, rax""",
|
||
op=[t.ASM_DESCR.CLOBBER_RAX])
|
||
c.Asm("fninit", op=[t.ASM_DESCR.CLOBBER_MEMORY])
|