TermiNexus
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内容由用户产出，本次仅代为提交、未做任何语义修改；含 static 修饰符前置迁移等（新增 static 前缀 16 行）。提交消息为中性描述——如需更精确的说明请 amend。
259 lines
9.3 KiB
Plaintext
259 lines
9.3 KiB
Plaintext
import asm
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import intr.gdt as gdt
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import intr.idt as idt
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import drivers.serial.uart.serial as serial
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import drivers.core.cpu.cpu as cpu
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import mm.mm as mm
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import platform.pch.timer as timer
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import viperlib
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define IA32_APIC_BASE = 0x1B
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define APIC_BASE_MSR_ENABLE = 0x800
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define APIC_BASE_ADDR_MASK = 0xFFFFF000
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define LAPIC_ID = 0x020
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define LAPIC_VERSION = 0x030
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define LAPIC_TPR = 0x080
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define LAPIC_EOI = 0x0B0
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define LAPIC_LDR = 0x0D0
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define LAPIC_SVR = 0x0F0
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define LAPIC_ISR0 = 0x100
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define LAPIC_ICR_LOW = 0x300
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define LAPIC_ICR_HIGH = 0x310
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define LAPIC_LVT_TIMER = 0x320
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define LAPIC_LVT_LINT0 = 0x350
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define LAPIC_LVT_LINT1 = 0x360
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define LAPIC_LVT_ERROR = 0x370
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define LAPIC_TIMER_INIT = 0x380
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define LAPIC_TIMER_CURRENT = 0x390
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define LAPIC_TIMER_DIVIDE = 0x3E0
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define LAPIC_SVR_ENABLE = 0x100
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define LAPIC_LVT_MASKED = 0x10000
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define LAPIC_LVT_DELIVERY_EXTINT = 0x700
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define LAPIC_LVT_DELIVERY_NMI = 0x400
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define LAPIC_LVT_TIMER_PERIODIC = 0x20000
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define LAPIC_ICR_INIT = 0x500
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define LAPIC_ICR_STARTUP = 0x600
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define LAPIC_ICR_ASSERT = 0x4000
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define LAPIC_ICR_DEASSERT = 0x8000
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define LAPIC_ICR_LEVEL = 0x8000
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define MAX_CPUS = 8
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define AP_TRAMPOLINE_ADDR = 0x7000
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# trampoline 机器码字节数
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define AP_TRAMPOLINE_LEN = 138
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_lapic_base: uint64 = 0
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_cpu_count: uint32 = 1
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_bsp_lapic_id: uint32 = 0
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_ap_ready: uint32 = 0
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def read(offset: uint32) -> uint32:
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addr: uint64 = _lapic_base + uint64(offset)
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return *(uint32*(addr))
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def write(offset: uint32, value: uint32):
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addr: uint64 = _lapic_base + uint64(offset)
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*(uint32*(addr)) = value
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def eoi():
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write(LAPIC_EOI, 0)
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def get_id() -> uint32:
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return read(LAPIC_ID) >> 24
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@__attribute__(noinline)
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def init():
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global _lapic_base, _bsp_lapic_id
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msr_val: uint64 = cpu.msr_read(IA32_APIC_BASE)
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_lapic_base = msr_val & APIC_BASE_ADDR_MASK
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cpu.msr_write(IA32_APIC_BASE, msr_val | APIC_BASE_MSR_ENABLE)
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_bsp_lapic_id = read(LAPIC_ID) >> 24
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write(LAPIC_SVR, LAPIC_SVR_ENABLE | 0xFF)
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write(LAPIC_TPR, 0)
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write(LAPIC_LVT_TIMER, LAPIC_LVT_MASKED)
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write(LAPIC_LVT_LINT0, LAPIC_LVT_DELIVERY_EXTINT)
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write(LAPIC_LVT_LINT1, LAPIC_LVT_DELIVERY_NMI)
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write(LAPIC_LVT_ERROR, LAPIC_LVT_MASKED)
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write(LAPIC_TIMER_DIVIDE, 0x0B)
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write(LAPIC_LDR, 0x01000000)
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eoi()
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@__attribute__(noinline)
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def detect_cpu_count() -> uint32:
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res: cpu.cpuid_result
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cpu.cpuid(0, &res)
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max_leaf: uint32 = res.eax
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if max_leaf >= 0x0B:
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cpu.cpuid_sub(0x0B, 0, &res)
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num_threads: uint32 = res.ebx & 0xFFFF
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if num_threads > 0 and num_threads <= MAX_CPUS:
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return num_threads
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cpu.cpuid(1, &res)
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if res.edx & cpu.CPU_FEATURE_HTT:
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count: uint32 = (res.ebx >> 16) & 0xFF
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if count > 0 and count <= MAX_CPUS:
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return count
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return 1
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def _wait_icr():
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timeout: uint32 = 1000000
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while timeout > 0:
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val: uint32 = read(LAPIC_ICR_LOW)
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if (val & (1 << 12)) == 0:
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return
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timeout -= 1
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def _send_ipi(apic_id: uint32, vector: uint32, delivery_mode: uint32):
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_wait_icr()
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write(LAPIC_ICR_HIGH, apic_id << 24)
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write(LAPIC_ICR_LOW, vector | delivery_mode | LAPIC_ICR_LEVEL | LAPIC_ICR_ASSERT)
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_wait_icr()
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def ap_entry():
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global _ap_ready
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my_id: uint32 = get_id()
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buf: [64]char
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viperlib.snprintf(&buf, 64, "[AP] core %u started (lapic=%u)\n", my_id, my_id)
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serial.puts(buf)
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_ap_ready = 1
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while True:
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asm.sti()
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asm.hlt()
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_trampoline_bin: [AP_TRAMPOLINE_LEN]uint8 = [
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0xFA, # cli
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0x31, 0xC0, # xor ax, ax
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x0F, 0x01, 0x16, 0x00, 0x7E, # lgdt [0x7E00]
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0x0F, 0x20, 0xC0, # mov eax, cr0
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0x83, 0xC8, 0x01, # or eax, 1
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0x0F, 0x22, 0xC0, # mov cr0, eax
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0xEA, 0x1A, 0x07, 0x00, 0x00, 0x08, 0x00, # jmp 0x08:0x701A
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# 32-bit 保护模式开始
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0xB8, 0x10, 0x00, 0x00, 0x00, # mov ax, 0x10
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x8E, 0xE0, # mov fs, ax
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0x8E, 0xE8, # mov gs, ax
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0x8E, 0xD0, # mov ss, ax
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0x0F, 0x20, 0xE0, # mov eax, cr4
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0x83, 0xC8, 0x20, # or eax, 0x20 (PAE)
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0x0F, 0x22, 0xE0, # mov cr4, eax
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0x8B, 0x04, 0x25, 0x00, 0x7F, 0x00, 0x00, # mov eax, [0x7F00]
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0x0F, 0x22, 0xD8, # mov cr3, eax
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0xB9, 0x80, 0x00, 0x00, 0xC0, # mov ecx, 0xC0000080 (EFER)
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0x0F, 0x32, # rdmsr
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# 0x83 C8 只能编码 1 字节立即数；0x100 须用 0x81 C8 imm32（6 字节）。
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# 原写 0x83 会把后 4 字节 00 01 00 00 当作下一条指令执行（N7）。
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0x81, 0xC8, 0x00, 0x01, 0x00, 0x00, # or eax, 0x100 (LME)
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0x0F, 0x79, # wrmsr
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0x0F, 0x20, 0xC0, # mov eax, cr0
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0x0D, 0x00, 0x00, 0x00, 0x80, # or eax, 0x80000000 (PG)
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0x0F, 0x22, 0xC0, # mov cr0, eax
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0xEA, 0x5A, 0x07, 0x00, 0x00, 0x08, 0x00, # jmp 0x08:0x705A
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# 64-bit 长模式开始
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0x48, 0x8B, 0x24, 0x25, 0x08, 0x7F, 0x00, 0x00, # mov rsp, [0x7F08]
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0x0F, 0x01, 0x16, 0x10, 0x7F, # lgdt [0x7F10]
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0x0F, 0x01, 0x1E, 0x20, 0x7F, # lidt [0x7F20]
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0xB8, 0x10, 0x00, 0x00, 0x00, # mov ax, 0x10
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0x8E, 0xD8, # mov ds, ax
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0x8E, 0xC0, # mov es, ax
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0x8E, 0xE0, # mov fs, ax
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0x8E, 0xE8, # mov gs, ax
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0x8E, 0xD0, # mov ss, ax
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0x48, 0x8B, 0x04, 0x25, 0x30, 0x7F, 0x00, 0x00, # mov rax, [0x7F30]
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0xFF, 0xE0 # jmp rax
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]
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def _setup_trampoline(entry_addr: uint64, stack_addr: uint64, cr3_val: uint64):
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dest: uint8* = uint8*(AP_TRAMPOLINE_ADDR)
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src: uint8* = &_trampoline_bin
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for i in range(AP_TRAMPOLINE_LEN):
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*(dest + uint64(i)) = *(src + uint64(i))
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gdt_ptr_addr: uint64 = AP_TRAMPOLINE_ADDR + 0x0E00
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*(uint16*(gdt_ptr_addr)) = uint16(23)
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*(uint64*(gdt_ptr_addr + 2)) = uint64(AP_TRAMPOLINE_ADDR + 0x0E10)
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gdt_addr: uint64 = AP_TRAMPOLINE_ADDR + 0x0E10
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*(uint64*(gdt_addr + 0)) = uint64(0)
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*(uint64*(gdt_addr + 8)) = uint64(0x00AF9A000000FFFF)
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*(uint64*(gdt_addr + 16)) = uint64(0x00CF92000000FFFF)
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*(uint32*(AP_TRAMPOLINE_ADDR + 0x0F00)) = uint32(cr3_val)
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*(uint64*(AP_TRAMPOLINE_ADDR + 0x0F08)) = stack_addr
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gp_addr: uint64 = uint64(&gdt.gp)
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gdt_base: uint64 = *(uint64*(gp_addr + 2))
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gdt_limit: uint16 = *(uint16*(gp_addr))
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*(uint16*(AP_TRAMPOLINE_ADDR + 0x0F10)) = gdt_limit
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*(uint64*(AP_TRAMPOLINE_ADDR + 0x0F12)) = gdt_base
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idt_addr: uint64 = uint64(&idt.idt)
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idt_base: uint64 = *(uint64*(idt_addr + 2))
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idt_limit: uint16 = *(uint16*(idt_addr))
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*(uint16*(AP_TRAMPOLINE_ADDR + 0x0F20)) = idt_limit
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*(uint64*(AP_TRAMPOLINE_ADDR + 0x0F22)) = idt_base
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# entry 槽位后移到 0x0F30：idt 伪描述符占 0x0F20..0x0F29（limit 2 + base 8），
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# 原来 entry 放 0x0F28 会与其 base 尾部 2 字节重叠 → lidt 读到被覆盖的基址。
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*(uint64*(AP_TRAMPOLINE_ADDR + 0x0F30)) = entry_addr
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def start_aps():
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global _cpu_count, _ap_ready
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if _cpu_count <= 1: return
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cr3_val: uint64 = 0
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__asm__(f"""mov rax, cr3
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mov {asmout(cr3_val, ASM_DESCR.OUTPUT_REG)}, rax""", op = [ASM_DESCR.CLOBBER_RAX])
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stack_size: uint64 = 8192
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for i in range(1, _cpu_count):
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_ap_ready = 0
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stack: rawptr = mm.malloc(stack_size)
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if stack is None: continue
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stack_top: uint64 = uint64(stack) + stack_size
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stack_top = stack_top & ~uint64(15)
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_setup_trampoline(uint64(ap_entry), stack_top, cr3_val)
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_send_ipi(i, 0, LAPIC_ICR_INIT)
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timer.timer_msleep(10)
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_send_ipi(i, (AP_TRAMPOLINE_ADDR >> 12) & 0xFF, LAPIC_ICR_STARTUP)
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timer.timer_msleep(1)
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_send_ipi(i, (AP_TRAMPOLINE_ADDR >> 12) & 0xFF, LAPIC_ICR_STARTUP)
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for i in range(5000):
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if _ap_ready != 0: break
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timer.timer_msleep(1)
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def early_init():
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global _cpu_count, _bsp_lapic_id
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# 直接以 IA32_APIC_BASE 的 EN 位(bit 11)判断 APIC 是否可用：
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# QEMU/OVMF 必启用，且 msr_read 路径已在前置流程验证可用；
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# 比依赖 cpuid 特性位更可靠（避免 cpuid 包装被误判时静默跳过 init）。
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msr_val: uint64 = cpu.msr_read(IA32_APIC_BASE)
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if msr_val & APIC_BASE_MSR_ENABLE:
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init()
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_cpu_count = detect_cpu_count()
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else:
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_cpu_count = 1
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def get_cpu_count() -> uint32:
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return _cpu_count
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def get_base() -> uint64:
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return _lapic_base
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def get_lapic_id() -> uint32:
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return get_id()
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